[Mesa-dev] [Mesa-stable] [PATCH 1/8] radv: don't flush src stages when dstStageMask == BOTTOM_OF_PIPE

[Andres Gomez]

Fredrik, which is the status of this series? Several patches got R-b
but nothing has landed so far. Are you in need of more reviews for the
rest of the patches in the series?

On Tue, 2018-06-26 at 23:49 +0200, Fredrik Höglund wrote:
> The Vulkan specification says:
> 
>    "An execution dependency with only VK_PIPELINE_STAGE_BOTTOM_OF_-
>     PIPE_BIT in the destination stage mask [...] does not delay
>     processing of subsequent commands."
> 
> Cc: <mesa-stable at lists.freedesktop.org>
> Signed-off-by: Fredrik Höglund <fredrik at kde.org>
> ---
>  src/amd/vulkan/radv_cmd_buffer.c | 3 ++-
>  src/amd/vulkan/radv_pass.c       | 6 ++++--
>  2 files changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
> index 110a9a960a9..5bfcba28d83 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -4197,7 +4197,8 @@ void radv_CmdPipelineBarrier(
>  		                                        image);
>  	}
>  
> -	radv_stage_flush(cmd_buffer, srcStageMask);
> +	if (destStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
> +		radv_stage_flush(cmd_buffer, srcStageMask);
>  	cmd_buffer->state.flush_bits |= src_flush_bits;
>  
>  	for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
> diff --git a/src/amd/vulkan/radv_pass.c b/src/amd/vulkan/radv_pass.c
> index 15fee444cdc..7a0dca09496 100644
> --- a/src/amd/vulkan/radv_pass.c
> +++ b/src/amd/vulkan/radv_pass.c
> @@ -174,11 +174,13 @@ VkResult radv_CreateRenderPass(
>  	for (unsigned i = 0; i < pCreateInfo->dependencyCount; ++i) {
>  		uint32_t dst = pCreateInfo->pDependencies[i].dstSubpass;
>  		if (dst == VK_SUBPASS_EXTERNAL) {
> -			pass->end_barrier.src_stage_mask = pCreateInfo->pDependencies[i].srcStageMask;
> +			if (pCreateInfo->pDependencies[i].dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
> +				pass->end_barrier.src_stage_mask = pCreateInfo->pDependencies[i].srcStageMask;
>  			pass->end_barrier.src_access_mask = pCreateInfo->pDependencies[i].srcAccessMask;
>  			pass->end_barrier.dst_access_mask = pCreateInfo->pDependencies[i].dstAccessMask;
>  		} else {
> -			pass->subpasses[dst].start_barrier.src_stage_mask = pCreateInfo->pDependencies[i].srcStageMask;
> +			if (pCreateInfo->pDependencies[i].dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
> +				pass->subpasses[dst].start_barrier.src_stage_mask = pCreateInfo->pDependencies[i].srcStageMask;
>  			pass->subpasses[dst].start_barrier.src_access_mask = pCreateInfo->pDependencies[i].srcAccessMask;
>  			pass->subpasses[dst].start_barrier.dst_access_mask = pCreateInfo->pDependencies[i].dstAccessMask;
>  		}
-- 
Br,

Andres