[Mesa-dev] [PATCH 00/22] intel: Do storage image lowering in NIR

[Jason Ekstrand]

This patch series has been on my mind to write for a very long time now.
It moves the storage image lowering we have to do for Intel hardware into
NIR.  This series makes several improvements:

 1) The NIR optimizer can go to town on it and we can just improve the
    optimizer instead of spending time carefully tuning our code-gen.

 2) It also provides a nice separation between the image references
    themselves and the parameters  we have to push into the shader for
    address calculations on BDW and earlier.  This has always bothered me
    in Vulkan because there we don't have a contiguous array of image slots
    like in GL.

 3) After this series, the binding table indices are passed directly into
    the dataport messages instead of being pulled from a uniform.  This
    should be more efficient and makes shaders easier to read.  It's also a
    good step in the direction of being able to start using bindless for
    images.

 4) On Sky Lake and above, brw_image_param is no longer needed at all.
    This will make Ken's life way easier as he tries to hook up images in
    the new Gallium driver.

This series is also available as a branch on GitLab:

https://gitlab.freedesktop.org/jekstrand/mesa/commits/review/nir-image-load-store


Jason Ekstrand (22):
  nir/algebraic: Be more careful converting ushr to extract_u8/16
  nir/algebraic: Add more extract_[iu](8|16) optimizations
  nir/algebraic: Add some max/min optimizations
  nir/opcodes: Make unpack_half_2x16_split_* variable-width
  nir/format_convert: Add support for unpacking signed integers
  nir/format_convert: Add vec mask and sign-extend helpers
  nir/format_convert: Rename nir_format_bitcast_uint_vec
  nir/format_convert: Add [us]norm conversion helpers
  nir/format_convert: Rename pack_r11g11b10f to pack_11f11f10f
  nir/format_convert: Fix a bitmask in unpack_11f11f10f
  nir: Make image load/store intrinsics variable-width
  anv/pipeline: Remove dead image loads in lower_input_attacnments
  nir/types: Add a wrapper for coordinate_components
  intel/compiler: Do image load/store lowering to NIR
  isl: Use the view array length for the image size
  intel/compiler: Use two components for 1D array image sizes
  glsl/link,i965: Make ImageAccess four-state
  intel: Use TXQ for image_size when we have a typed surface
  nir: Use a bitfield for image access qualifiers
  nir: Add handle/index-based image intrinsics
  anv,i965: Lower away image derefs in the driver
  intel/compiler: Remove surface_idx from brw_image_param

 src/amd/common/ac_nir_to_llvm.c               |    4 +-
 src/compiler/glsl/gl_nir_link_uniforms.c      |   10 +-
 src/compiler/glsl/glsl_to_nir.cpp             |   28 +-
 src/compiler/glsl/link_uniforms.cpp           |    8 +-
 src/compiler/nir/nir.h                        |   36 +-
 src/compiler/nir/nir_format_convert.h         |  137 ++-
 src/compiler/nir/nir_intrinsics.py            |   57 +-
 src/compiler/nir/nir_opcodes.py               |    8 +-
 src/compiler/nir/nir_opt_algebraic.py         |   20 +-
 src/compiler/nir/nir_print.c                  |   33 +-
 src/compiler/nir_types.cpp                    |    7 +
 src/compiler/nir_types.h                      |    1 +
 src/compiler/shader_enums.h                   |   10 +-
 src/compiler/spirv/spirv_to_nir.c             |    2 +
 src/compiler/spirv/vtn_variables.c            |   10 +-
 src/intel/Makefile.sources                    |    1 +
 src/intel/blorp/blorp_blit.c                  |    2 +-
 src/intel/compiler/brw_compiler.h             |   16 +-
 src/intel/compiler/brw_eu_defines.h           |    3 +
 src/intel/compiler/brw_fs.cpp                 |   18 +-
 src/intel/compiler/brw_fs.h                   |    3 +-
 src/intel/compiler/brw_fs_generator.cpp       |   26 +-
 src/intel/compiler/brw_fs_nir.cpp             |  319 +++--
 src/intel/compiler/brw_fs_surface_builder.cpp | 1030 -----------------
 src/intel/compiler/brw_fs_surface_builder.h   |   20 -
 src/intel/compiler/brw_nir.h                  |    8 +
 .../compiler/brw_nir_lower_image_load_store.c |  867 ++++++++++++++
 src/intel/compiler/brw_shader.cpp             |    5 +
 src/intel/compiler/meson.build                |    1 +
 src/intel/isl/isl_storage_image.c             |   17 +-
 .../vulkan/anv_nir_apply_pipeline_layout.c    |  160 ++-
 .../vulkan/anv_nir_lower_input_attachments.c  |    4 +-
 src/intel/vulkan/anv_pipeline.c               |    2 +
 src/intel/vulkan/genX_cmd_buffer.c            |    2 -
 .../drivers/dri/i965/brw_nir_uniforms.cpp     |  133 ++-
 src/mesa/drivers/dri/i965/brw_program.c       |    3 +
 .../drivers/dri/i965/brw_wm_surface_state.c   |   24 +-
 src/mesa/main/mtypes.h                        |    9 +-
 38 files changed, 1630 insertions(+), 1414 deletions(-)
 create mode 100644 src/intel/compiler/brw_nir_lower_image_load_store.c

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2.17.1