[Mesa-dev] [PATCH] i965/icl: Allow headerless sampler messages for pre-emptable contexts

[Anuj Phogat]

On Mon, Aug 20, 2018 at 12:18 AM Kenneth Graunke <kenneth at whitecape.org> wrote:
>
> On Friday, August 17, 2018 5:13:25 PM PDT Anuj Phogat wrote:
> > It fixes simulator warnings in piglit tests complaining about missing
> > support for headerless sampler messages for pre-emptable contexts.
> > Bit 5 in SAMPLER MODE register is newly introduced for ICLLP.
> >
> > Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
> > ---
> >  src/mesa/drivers/dri/i965/brw_defines.h      |  4 ++++
> >  src/mesa/drivers/dri/i965/brw_state_upload.c | 11 +++++++++++
> >  2 files changed, 15 insertions(+)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
> > index 855f1c7d744..433314115b1 100644
> > --- a/src/mesa/drivers/dri/i965/brw_defines.h
> > +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> > @@ -1673,4 +1673,8 @@ enum brw_pixel_shader_coverage_mask_mode {
> >  # define GLK_SCEC_BARRIER_MODE_3D_HULL     (1 << 7)
> >  # define GLK_SCEC_BARRIER_MODE_MASK        REG_MASK(1 << 7)
> >
> > +#define GEN11_SAMPLER_MODE                                  0xE18C
> > +# define HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS        (1 << 5)
> > +# define HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS_MASK   REG_MASK(1 << 5)
> > +
> >  #endif
> > diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
> > index 757426407c3..5a334b48892 100644
> > --- a/src/mesa/drivers/dri/i965/brw_state_upload.c
> > +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
> > @@ -63,6 +63,17 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
> >
> >     brw_upload_invariant_state(brw);
> >
> > +   if (devinfo->gen == 11) {
> > +      /*  The default behavior of bit 5 "Headerless Message for Pre-emptable
> > +       *  Contexts" in SAMPLER MODE register is set to 0, which means
> > +       *  headerless sampler messages are not allowed for pre-emptable
> > +       *  contexts. Set the bit 5 to 1 to allow them.
>
> Bonus space after the stars.  Can we also change this to:
>
>        * contexts.  Set bit 5 to allow them.
>
> Same for the anv patch.  Either way, both are:
> Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
>
Fixed locally. Thanks.
> I don't know if people are trying to enable pre-emption during GPGPU
> work on pre-Gen11.  If so, that probably will not work, and we'd either
> need to avoid headerless messages (gross) or disable preemption (maybe
> also bad...)
>
Why do you think it'll be problem for Pre-Gen11? I don't see a bit disallowing
preemption+headerless message for pre-Gen11.

> > +       */
> > +      brw_load_register_imm32(brw, GEN11_SAMPLER_MODE,
> > +                              HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS_MASK |
> > +                              HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS);
> > +   }
> > +
> >     if (devinfo->gen == 10 || devinfo->gen == 11) {
> >        /* From gen10 workaround table in h/w specs:
> >         *
> >
>