[Mesa-dev] [PATCH 1/7] gallium: add TGSI_MEMORY_STREAM_CACHE_POLICY

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

For internal radeonsi shaders.
---
 src/gallium/auxiliary/tgsi/tgsi_strings.c         | 3 ++-
 src/gallium/auxiliary/tgsi/tgsi_strings.h         | 2 +-
 src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c | 3 +++
 src/gallium/include/pipe/p_shader_tokens.h        | 8 ++++++--
 4 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_strings.c b/src/gallium/auxiliary/tgsi/tgsi_strings.c
index 434871273f2..03261ed2d99 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_strings.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_strings.c
@@ -221,25 +221,26 @@ const char *tgsi_fs_coord_pixel_center_names[2] =
 const char *tgsi_immediate_type_names[6] =
 {
    "FLT32",
    "UINT32",
    "INT32",
    "FLT64",
    "UINT64",
    "INT64",
 };
 
-const char *tgsi_memory_names[3] =
+const char *tgsi_memory_names[4] =
 {
    "COHERENT",
    "RESTRICT",
    "VOLATILE",
+   "STREAM_CACHE_POLICY",
 };
 
 
 static inline void
 tgsi_strings_check(void)
 {
    STATIC_ASSERT(ARRAY_SIZE(tgsi_semantic_names) == TGSI_SEMANTIC_COUNT);
    STATIC_ASSERT(ARRAY_SIZE(tgsi_texture_names) == TGSI_TEXTURE_COUNT);
    STATIC_ASSERT(ARRAY_SIZE(tgsi_property_names) == TGSI_PROPERTY_COUNT);
    STATIC_ASSERT(ARRAY_SIZE(tgsi_primitive_names) == PIPE_PRIM_MAX);
diff --git a/src/gallium/auxiliary/tgsi/tgsi_strings.h b/src/gallium/auxiliary/tgsi/tgsi_strings.h
index 20e3f7127f6..61068d562d8 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_strings.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_strings.h
@@ -55,21 +55,21 @@ extern const char *tgsi_interpolate_locations[TGSI_INTERPOLATE_LOC_COUNT];
 extern const char *tgsi_invariant_name;
 
 extern const char *tgsi_primitive_names[PIPE_PRIM_MAX];
 
 extern const char *tgsi_fs_coord_origin_names[2];
 
 extern const char *tgsi_fs_coord_pixel_center_names[2];
 
 extern const char *tgsi_immediate_type_names[6];
 
-extern const char *tgsi_memory_names[3];
+extern const char *tgsi_memory_names[4];
 
 
 const char *
 tgsi_file_name(unsigned file);
 
 
 #if defined __cplusplus
 }
 #endif
 
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
index 8e0578b4d5e..eaa200a95d6 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
@@ -324,20 +324,23 @@ static unsigned get_cache_policy(struct si_shader_context *ctx,
 	     * The only way to get unaligned stores in radeonsi is through
 	     * shader images. */
 	    ((may_store_unaligned && ctx->screen->info.chip_class == SI) ||
 	     /* If this is write-only, don't keep data in L1 to prevent
 	      * evicting L1 cache lines that may be needed by other
 	      * instructions. */
 	     writeonly_memory ||
 	     inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE)))
 		cache_policy |= ac_glc;
 
+	if (inst->Memory.Qualifier & TGSI_MEMORY_STREAM_CACHE_POLICY)
+		cache_policy |= ac_slc;
+
 	return cache_policy;
 }
 
 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
                                    const struct tgsi_full_instruction *inst,
                                    LLVMTypeRef type, int arg)
 {
 	LLVMBuilderRef builder = ctx->ac.builder;
 	LLVMValueRef offset, ptr;
 	int addr_space;
diff --git a/src/gallium/include/pipe/p_shader_tokens.h b/src/gallium/include/pipe/p_shader_tokens.h
index 08ed08156e7..bef826f23b5 100644
--- a/src/gallium/include/pipe/p_shader_tokens.h
+++ b/src/gallium/include/pipe/p_shader_tokens.h
@@ -783,30 +783,34 @@ struct tgsi_dst_register
    unsigned WriteMask   : 4;  /* TGSI_WRITEMASK_ */
    unsigned Indirect    : 1;  /* BOOL */
    unsigned Dimension   : 1;  /* BOOL */
    int      Index       : 16; /* SINT */
    unsigned Padding     : 6;
 };
 
 #define TGSI_MEMORY_COHERENT (1 << 0)
 #define TGSI_MEMORY_RESTRICT (1 << 1)
 #define TGSI_MEMORY_VOLATILE (1 << 2)
+/* The "stream" cache policy will minimize memory cache usage if other
+ * memory operations need the cache.
+ */
+#define TGSI_MEMORY_STREAM_CACHE_POLICY (1 << 3)
 
 /**
  * Specifies the type of memory access to do for the LOAD/STORE instruction.
  */
 struct tgsi_instruction_memory
 {
-   unsigned Qualifier : 3;  /* TGSI_MEMORY_ */
+   unsigned Qualifier : 4;  /* TGSI_MEMORY_ */
    unsigned Texture   : 8;  /* only for images: TGSI_TEXTURE_ */
    unsigned Format    : 10; /* only for images: PIPE_FORMAT_ */
-   unsigned Padding   : 11;
+   unsigned Padding   : 10;
 };
 
 #define TGSI_MEMBAR_SHADER_BUFFER (1 << 0)
 #define TGSI_MEMBAR_ATOMIC_BUFFER (1 << 1)
 #define TGSI_MEMBAR_SHADER_IMAGE  (1 << 2)
 #define TGSI_MEMBAR_SHARED        (1 << 3)
 #define TGSI_MEMBAR_THREAD_GROUP  (1 << 4)
 
 #ifdef __cplusplus
 }
-- 
2.17.1