[Mesa-dev] [PATCH 4/7] radeonsi: add SI_QUERY_TIME_ELAPSED_SDMA_SI for measuring DMA on SI

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

DMA on SI doesn't support the timestamp packet, so it's emulated.
---
 src/gallium/drivers/radeonsi/si_query.c | 19 +++++++++++++++++++
 src/gallium/drivers/radeonsi/si_query.h |  1 +
 2 files changed, 20 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_query.c b/src/gallium/drivers/radeonsi/si_query.c
index 93efbd4ef4a..80e84c23937 100644
--- a/src/gallium/drivers/radeonsi/si_query.c
+++ b/src/gallium/drivers/radeonsi/si_query.c
@@ -85,30 +85,46 @@ static enum radeon_value_id winsys_id_from_type(unsigned type)
 	case SI_QUERY_VRAM_VIS_USAGE: return RADEON_VRAM_VIS_USAGE;
 	case SI_QUERY_GTT_USAGE: return RADEON_GTT_USAGE;
 	case SI_QUERY_GPU_TEMPERATURE: return RADEON_GPU_TEMPERATURE;
 	case SI_QUERY_CURRENT_GPU_SCLK: return RADEON_CURRENT_SCLK;
 	case SI_QUERY_CURRENT_GPU_MCLK: return RADEON_CURRENT_MCLK;
 	case SI_QUERY_CS_THREAD_BUSY: return RADEON_CS_THREAD_TIME;
 	default: unreachable("query type does not correspond to winsys id");
 	}
 }
 
+static int64_t si_finish_dma_get_cpu_time(struct si_context *sctx)
+{
+	struct pipe_fence_handle *fence = NULL;
+
+	si_flush_dma_cs(sctx, 0, &fence);
+	if (fence) {
+		sctx->ws->fence_wait(sctx->ws, fence, PIPE_TIMEOUT_INFINITE);
+		sctx->ws->fence_reference(&fence, NULL);
+	}
+
+	return os_time_get_nano();
+}
+
 static bool si_query_sw_begin(struct si_context *sctx,
 			      struct si_query *rquery)
 {
 	struct si_query_sw *query = (struct si_query_sw *)rquery;
 	enum radeon_value_id ws_id;
 
 	switch(query->b.type) {
 	case PIPE_QUERY_TIMESTAMP_DISJOINT:
 	case PIPE_QUERY_GPU_FINISHED:
 		break;
+	case SI_QUERY_TIME_ELAPSED_SDMA_SI:
+		query->begin_result = si_finish_dma_get_cpu_time(sctx);
+		break;
 	case SI_QUERY_DRAW_CALLS:
 		query->begin_result = sctx->num_draw_calls;
 		break;
 	case SI_QUERY_DECOMPRESS_CALLS:
 		query->begin_result = sctx->num_decompress_calls;
 		break;
 	case SI_QUERY_MRT_DRAW_CALLS:
 		query->begin_result = sctx->num_mrt_draw_calls;
 		break;
 	case SI_QUERY_PRIM_RESTART_CALLS:
@@ -255,20 +271,23 @@ static bool si_query_sw_end(struct si_context *sctx,
 {
 	struct si_query_sw *query = (struct si_query_sw *)rquery;
 	enum radeon_value_id ws_id;
 
 	switch(query->b.type) {
 	case PIPE_QUERY_TIMESTAMP_DISJOINT:
 		break;
 	case PIPE_QUERY_GPU_FINISHED:
 		sctx->b.flush(&sctx->b, &query->fence, PIPE_FLUSH_DEFERRED);
 		break;
+	case SI_QUERY_TIME_ELAPSED_SDMA_SI:
+		query->end_result = si_finish_dma_get_cpu_time(sctx);
+		break;
 	case SI_QUERY_DRAW_CALLS:
 		query->end_result = sctx->num_draw_calls;
 		break;
 	case SI_QUERY_DECOMPRESS_CALLS:
 		query->end_result = sctx->num_decompress_calls;
 		break;
 	case SI_QUERY_MRT_DRAW_CALLS:
 		query->end_result = sctx->num_mrt_draw_calls;
 		break;
 	case SI_QUERY_PRIM_RESTART_CALLS:
diff --git a/src/gallium/drivers/radeonsi/si_query.h b/src/gallium/drivers/radeonsi/si_query.h
index bc3eb397bc5..cf2eccd862b 100644
--- a/src/gallium/drivers/radeonsi/si_query.h
+++ b/src/gallium/drivers/radeonsi/si_query.h
@@ -103,20 +103,21 @@ enum {
 	SI_QUERY_NUM_COMPILATIONS,
 	SI_QUERY_NUM_SHADERS_CREATED,
 	SI_QUERY_BACK_BUFFER_PS_DRAW_RATIO,
 	SI_QUERY_NUM_SHADER_CACHE_HITS,
 	SI_QUERY_GPIN_ASIC_ID,
 	SI_QUERY_GPIN_NUM_SIMD,
 	SI_QUERY_GPIN_NUM_RB,
 	SI_QUERY_GPIN_NUM_SPI,
 	SI_QUERY_GPIN_NUM_SE,
 	SI_QUERY_TIME_ELAPSED_SDMA,
+	SI_QUERY_TIME_ELAPSED_SDMA_SI, /* emulated, measured on the CPU */
 
 	SI_QUERY_FIRST_PERFCOUNTER = PIPE_QUERY_DRIVER_SPECIFIC + 100,
 };
 
 enum {
 	SI_QUERY_GROUP_GPIN = 0,
 	SI_NUM_SW_QUERY_GROUPS
 };
 
 struct si_query_ops {
-- 
2.17.1