[Mesa-dev] [PATCH] anv/icl: Set Enabled Texel Offset Precision Fix bit

[Anuj Phogat]

h/w specification requires this bit to be always set.

Suggested-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
---
 src/intel/genxml/gen11.xml    |  5 +++++
 src/intel/vulkan/genX_state.c | 14 ++++++++++++++
 2 files changed, 19 insertions(+)

diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index 1b3befbbfc9..c69d7dc89c2 100644
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -3640,4 +3640,9 @@
     <field name="Headerless Message for Pre-emptable Contexts Mask" start="21" end="21" type="bool"/>
   </register>
 
+  <register name="HALF_SLICE_CHICKEN7" length="1" num="0x0e194">
+    <field name="Enabled Texel Offset Precision Fix" start="1" end="1" type="bool"/>
+    <field name="Enabled Texel Offset Precision Fix Mask" start="17" end="17" type="bool"/>
+  </register>
+
 </genxml>
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index d6ccd21524c..2f48a7e1995 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -172,6 +172,20 @@ genX(init_device_state)(struct anv_device *device)
       lri.RegisterOffset = GENX(SAMPLER_MODE_num);
       lri.DataDWord      = sampler_mode;
    }
+
+   /* Bit 1 "Enabled Texel Offset Precision Fix" must be set in
+    * HALF_SLICE_CHICKEN7 register.
+    */
+   uint32_t half_slice_chicken7;
+   anv_pack_struct(&half_slice_chicken7, GENX(HALF_SLICE_CHICKEN7),
+                   .EnabledTexelOffsetPrecisionFix = true,
+                   .EnabledTexelOffsetPrecisionFixMask = true);
+
+    anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
+      lri.RegisterOffset = GENX(HALF_SLICE_CHICKEN7_num);
+      lri.DataDWord      = half_slice_chicken7;
+   }
+
 #endif
 
    /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so
-- 
2.17.1