[Mesa-dev] [PATCH 01/15] radeonsi: fix HTILE for NPOT textures with mipmapping on SI/CI

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

VI uses addrlib so it's unaffected.

Cc: 18.1 18.2 <mesa-stable at lists.freedesktop.org>
---
 src/gallium/drivers/radeonsi/si_texture.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index e55fd815264..bcff226a586 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -924,22 +924,22 @@ static void si_texture_get_htile_size(struct si_screen *sscreen,
 		break;
 	case 16:
 		cl_width = 128;
 		cl_height = 64;
 		break;
 	default:
 		assert(0);
 		return;
 	}
 
-	width = align(tex->buffer.b.b.width0, cl_width * 8);
-	height = align(tex->buffer.b.b.height0, cl_height * 8);
+	width = align(tex->surface.u.legacy.level[0].nblk_x, cl_width * 8);
+	height = align(tex->surface.u.legacy.level[0].nblk_y, cl_height * 8);
 
 	slice_elements = (width * height) / (8 * 8);
 	slice_bytes = slice_elements * 4;
 
 	pipe_interleave_bytes = sscreen->info.pipe_interleave_bytes;
 	base_align = num_pipes * pipe_interleave_bytes;
 
 	tex->surface.htile_alignment = base_align;
 	tex->surface.htile_size =
 		util_num_layers(&tex->buffer.b.b, 0) *
-- 
2.17.1