[Mesa-dev] [PATCH 13/15] radeonsi: adjust and simplify max_alloc_size determination

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/amd/common/ac_gpu_info.c                     | 16 ++++++++--------
 .../winsys/radeon/drm/radeon_drm_winsys.c        |  8 +++++---
 2 files changed, 13 insertions(+), 11 deletions(-)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index bfaff45219f..766ad835476 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -248,23 +248,20 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 		r = amdgpu_query_info(dev, AMDGPU_INFO_MEMORY, sizeof(meminfo), &meminfo);
 		if (r) {
 			fprintf(stderr, "amdgpu: amdgpu_query_info(memory) failed.\n");
 			return false;
 		}
 
 		/* Note: usable_heap_size values can be random and can't be relied on. */
 		info->gart_size = meminfo.gtt.total_heap_size;
 		info->vram_size = meminfo.vram.total_heap_size;
 		info->vram_vis_size = meminfo.cpu_accessible_vram.total_heap_size;
-
-		info->max_alloc_size = MAX2(meminfo.vram.max_allocation,
-					    meminfo.gtt.max_allocation);
 	} else {
 		/* This is a deprecated interface, which reports usable sizes
 		 * (total minus pinned), but the pinned size computation is
 		 * buggy, so the values returned from these functions can be
 		 * random.
 		 */
 		struct amdgpu_heap_info vram, vram_vis, gtt;
 
 		r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
 		if (r) {
@@ -282,25 +279,20 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 
 		r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_GTT, 0, &gtt);
 		if (r) {
 			fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
 			return false;
 		}
 
 		info->gart_size = gtt.heap_size;
 		info->vram_size = vram.heap_size;
 		info->vram_vis_size = vram_vis.heap_size;
-
-		/* The kernel can split large buffers in VRAM but not in GTT, so large
-		 * allocations can fail or cause buffer movement failures in the kernel.
-		 */
-		info->max_alloc_size = MAX2(info->vram_size * 0.9, info->gart_size * 0.7);
 	}
 
 	/* Set chip identification. */
 	info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */
 	info->vce_harvest_config = amdinfo->vce_harvest_config;
 
 	switch (info->pci_id) {
 #define CHIPSET(pci_id, cfamily) \
 	case pci_id: \
 		info->family = CHIP_##cfamily; \
@@ -324,20 +316,28 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 		info->chip_class = SI;
 	else {
 		fprintf(stderr, "amdgpu: Unknown family.\n");
 		return false;
 	}
 
 	/* Set which chips have dedicated VRAM. */
 	info->has_dedicated_vram =
 		!(amdinfo->ids_flags & AMDGPU_IDS_FLAGS_FUSION);
 
+	/* The kernel can split large buffers in VRAM but not in GTT, so large
+	 * allocations can fail or cause buffer movement failures in the kernel.
+	 */
+	if (info->has_dedicated_vram)
+		info->max_alloc_size = info->vram_size * 0.8;
+	else
+		info->max_alloc_size = info->gart_size * 0.7;
+
 	/* Set hardware information. */
 	info->gds_size = gds.gds_total_size;
 	info->gds_gfx_partition_size = gds.gds_gfx_partition_size;
 	/* convert the shader clock from KHz to MHz */
 	info->max_shader_clock = amdinfo->max_engine_clk / 1000;
 	info->num_tcc_blocks = device_info.num_tcc_blocks;
 	info->max_se = amdinfo->num_shader_engines;
 	info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
 	info->has_hw_decode =
 		(uvd.available_rings != 0) || (vcn_dec.available_rings != 0);
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 343c80c600f..0c41e1397c7 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -354,25 +354,27 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
     }
     ws->info.gart_size = gem_info.gart_size;
     ws->info.vram_size = gem_info.vram_size;
     ws->info.vram_vis_size = gem_info.vram_visible;
     /* Older versions of the kernel driver reported incorrect values, and
      * didn't support more than 256MB of visible VRAM anyway
      */
     if (ws->info.drm_minor < 49)
         ws->info.vram_vis_size = MIN2(ws->info.vram_vis_size, 256*1024*1024);
 
-    /* Radeon allocates all buffers as contigous, which makes large allocations
+    /* Radeon allocates all buffers contiguously, which makes large allocations
      * unlikely to succeed. */
-    ws->info.max_alloc_size = MAX2(ws->info.vram_size, ws->info.gart_size) * 0.7;
     if (ws->info.has_dedicated_vram)
-        ws->info.max_alloc_size = MIN2(ws->info.vram_size * 0.7, ws->info.max_alloc_size);
+	    ws->info.max_alloc_size = ws->info.vram_size * 0.7;
+    else
+	    ws->info.max_alloc_size = ws->info.gart_size * 0.7;
+
     if (ws->info.drm_minor < 40)
         ws->info.max_alloc_size = MIN2(ws->info.max_alloc_size, 256*1024*1024);
     /* Both 32-bit and 64-bit address spaces only have 4GB. */
     ws->info.max_alloc_size = MIN2(ws->info.max_alloc_size, 3ull*1024*1024*1024);
 
     /* Get max clock frequency info and convert it to MHz */
     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SCLK, NULL,
                          &ws->info.max_shader_clock);
     ws->info.max_shader_clock /= 1000;
 
-- 
2.17.1