[Mesa-dev] [PATCH v2] anv/blorp: Do more flushing around HiZ clears

[Nanley Chery]

On Fri, Aug 31, 2018 at 05:15:53PM -0500, Jason Ekstrand wrote:
> We make the flush after a HiZ clear unconditional and add a flush/stall
> before the clear as well.
> 
> Cc: mesa-stable at lists.freedesktop.org
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107760
> ---
>  src/intel/vulkan/anv_blorp.c | 44 +++++++++++++++++++++++++++---------
>  1 file changed, 33 insertions(+), 11 deletions(-)
> 
> diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
> index 35b304f92b3..04bca4d261f 100644
> --- a/src/intel/vulkan/anv_blorp.c
> +++ b/src/intel/vulkan/anv_blorp.c
> @@ -1604,6 +1604,24 @@ anv_image_hiz_clear(struct anv_cmd_buffer *cmd_buffer,
>                                     ISL_AUX_USAGE_NONE, &stencil);
>     }
>  
> +   /* From the Sky Lake PRM Volume 7, "Depth Buffer Clear":
> +    *
> +    *    "The following is required when performing a depth buffer clear with
> +    *    using the WM_STATE or 3DSTATE_WM:
> +    *
> +    *       * If other rendering operations have preceded this clear, a
> +    *         PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
> +    *         enabled must be issued before the rectangle primitive used for
> +    *         the depth buffer clear operation.
> +    *       * [...]"
> +    *
> +    * Even though the PRM only says that this is required if using 3DSTATE_WM
> +    * and a 3DPRIMITIVE, it appears to also sometimes hang when doing a clear
> +    * with WM_HZ_OP.
			   ^
This part was a little hard to parse because the PRM hasn't mentioned
the hardware hanging and the subject's changed from the pipecontrol to
the GPU. Maybe replace it with something like the following?

			   the GPU appears to also need this to avoid
			   occasional hangs when doing a clear with
			   WM_HZ_OP.

We could discuss it more on IRC if you prefer.

With that changed, this patch is
Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>


> +    */
> +   cmd_buffer->state.pending_pipe_bits |=
> +      ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_DEPTH_STALL_BIT;
> +
>     blorp_hiz_clear_depth_stencil(&batch, &depth, &stencil,
>                                   level, base_layer, layer_count,
>                                   area.offset.x, area.offset.y,
> @@ -1618,18 +1636,22 @@ anv_image_hiz_clear(struct anv_cmd_buffer *cmd_buffer,
>  
>     /* From the SKL PRM, Depth Buffer Clear:
>      *
> -    * Depth Buffer Clear Workaround
> -    * Depth buffer clear pass using any of the methods (WM_STATE, 3DSTATE_WM
> -    * or 3DSTATE_WM_HZ_OP) must be followed by a PIPE_CONTROL command with
> -    * DEPTH_STALL bit and Depth FLUSH bits “set” before starting to render.
> -    * DepthStall and DepthFlush are not needed between consecutive depth clear
> -    * passes nor is it required if the depth-clear pass was done with
> -    * “full_surf_clear” bit set in the 3DSTATE_WM_HZ_OP.
> +    *    "Depth Buffer Clear Workaround
> +    *
> +    *    Depth buffer clear pass using any of the methods (WM_STATE,
> +    *    3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a PIPE_CONTROL
> +    *    command with DEPTH_STALL bit and Depth FLUSH bits “set” before
> +    *    starting to render.  DepthStall and DepthFlush are not needed between
> +    *    consecutive depth clear passes nor is it required if the depth-clear
> +    *    pass was done with “full_surf_clear” bit set in the
> +    *    3DSTATE_WM_HZ_OP."
> +    *
> +    * Even though the PRM provides a bunch of conditions under which this is
> +    * supposedly unnecessary, we choose to perform the flush unconditionally
> +    * just to be safe.
>      */
> -   if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
> -      cmd_buffer->state.pending_pipe_bits |=
> -         ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_DEPTH_STALL_BIT;
> -   }
> +   cmd_buffer->state.pending_pipe_bits |=
> +      ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_DEPTH_STALL_BIT;
>  }
>  
>  void
> -- 
> 2.17.1
> 
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