[Mesa-dev] [PATCH 10/25] radeonsi: extract declare_vs_blit_inputs

[Nicolai Hähnle]

From: Nicolai Hähnle <nicolai.haehnle at amd.com>

Prepare for some later refactoring.
---
 src/gallium/drivers/radeonsi/si_shader.c | 43 ++++++++++++++----------
 1 file changed, 25 insertions(+), 18 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index d455fb5db6a..1bc32f31020 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -4577,20 +4577,44 @@ static void declare_vs_input_vgprs(struct si_shader_context *ctx,
 
 	if (!shader->is_gs_copy_shader) {
 		/* Vertex load indices. */
 		ctx->param_vertex_index0 = fninfo->num_params;
 		for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
 			add_arg(fninfo, ARG_VGPR, ctx->i32);
 		*num_prolog_vgprs += shader->selector->info.num_inputs;
 	}
 }
 
+static void declare_vs_blit_inputs(struct si_shader_context *ctx,
+				   struct si_function_info *fninfo,
+				   unsigned vs_blit_property)
+{
+	ctx->param_vs_blit_inputs = fninfo->num_params;
+	add_arg(fninfo, ARG_SGPR, ctx->i32); /* i16 x1, y1 */
+	add_arg(fninfo, ARG_SGPR, ctx->i32); /* i16 x2, y2 */
+	add_arg(fninfo, ARG_SGPR, ctx->f32); /* depth */
+
+	if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
+		add_arg(fninfo, ARG_SGPR, ctx->f32); /* color0 */
+		add_arg(fninfo, ARG_SGPR, ctx->f32); /* color1 */
+		add_arg(fninfo, ARG_SGPR, ctx->f32); /* color2 */
+		add_arg(fninfo, ARG_SGPR, ctx->f32); /* color3 */
+	} else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
+		add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.x1 */
+		add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.y1 */
+		add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.x2 */
+		add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.y2 */
+		add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.z */
+		add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.w */
+	}
+}
+
 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
 				    struct si_function_info *fninfo)
 {
 	ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
 	ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
 	ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
 	add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tes_patch_id);
 }
 
 enum {
@@ -4621,38 +4645,21 @@ static void create_function(struct si_shader_context *ctx)
 			type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
 	}
 
 	LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
 
 	switch (type) {
 	case PIPE_SHADER_VERTEX:
 		declare_global_desc_pointers(ctx, &fninfo);
 
 		if (vs_blit_property) {
-			ctx->param_vs_blit_inputs = fninfo.num_params;
-			add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x1, y1 */
-			add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x2, y2 */
-			add_arg(&fninfo, ARG_SGPR, ctx->f32); /* depth */
-
-			if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
-				add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color0 */
-				add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color1 */
-				add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color2 */
-				add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color3 */
-			} else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
-				add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x1 */
-				add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y1 */
-				add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x2 */
-				add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y2 */
-				add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.z */
-				add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.w */
-			}
+			declare_vs_blit_inputs(ctx, &fninfo, vs_blit_property);
 
 			/* VGPRs */
 			declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
 			break;
 		}
 
 		declare_per_stage_desc_pointers(ctx, &fninfo, true);
 		declare_vs_specific_input_sgprs(ctx, &fninfo);
 		ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
 			ac_array_in_const32_addr_space(ctx->v4i32));
-- 
2.19.1