[Mesa-dev] [PATCH 08/11] intel/nir: provide SSA form to KHR_debug
Mark Janes
mark.a.janes at intel.com
Fri Dec 7 00:35:49 UTC 2018
---
src/intel/compiler/brw_fs.cpp | 11 ++++-----
src/intel/compiler/brw_nir.c | 26 +++++++++++++++++-----
src/intel/compiler/brw_nir.h | 1 +
src/intel/compiler/brw_shader.cpp | 2 +-
src/intel/compiler/brw_vec4.cpp | 2 +-
src/intel/compiler/brw_vec4_gs_visitor.cpp | 2 +-
src/intel/compiler/brw_vec4_tcs.cpp | 2 +-
7 files changed, 32 insertions(+), 14 deletions(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 43b920ae33d..f361d7aad9d 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -7139,7 +7139,7 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
if (!key->multisample_fbo)
NIR_PASS_V(shader, demote_sample_qualifiers);
NIR_PASS_V(shader, move_interpolation_to_top);
- shader = brw_postprocess_nir(shader, compiler, true);
+ shader = brw_postprocess_nir(shader, compiler, log_data, true);
/* key->alpha_test_func means simulating alpha testing via discards,
* so the shader definitely kills pixels.
@@ -7384,6 +7384,7 @@ cs_set_simd_size(struct brw_cs_prog_data *cs_prog_data, unsigned size)
static nir_shader *
compile_cs_to_nir(const struct brw_compiler *compiler,
+ void *log_data,
void *mem_ctx,
const struct brw_cs_prog_key *key,
const nir_shader *src_shader,
@@ -7392,7 +7393,7 @@ compile_cs_to_nir(const struct brw_compiler *compiler,
nir_shader *shader = nir_shader_clone(mem_ctx, src_shader);
shader = brw_nir_apply_sampler_key(shader, compiler, &key->tex, true);
brw_nir_lower_cs_intrinsics(shader, dispatch_width);
- return brw_postprocess_nir(shader, compiler, true);
+ return brw_postprocess_nir(shader, compiler, log_data, true);
}
const unsigned *
@@ -7425,7 +7426,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data,
/* Now the main event: Visit the shader IR and generate our CS IR for it.
*/
if (min_dispatch_width <= 8) {
- nir_shader *nir8 = compile_cs_to_nir(compiler, mem_ctx, key,
+ nir_shader *nir8 = compile_cs_to_nir(compiler, log_data, mem_ctx, key,
src_shader, 8);
v8 = new fs_visitor(compiler, log_data, mem_ctx, key, &prog_data->base,
NULL, /* Never used in core profile */
@@ -7446,7 +7447,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data,
if (likely(!(INTEL_DEBUG & DEBUG_NO16)) &&
!fail_msg && min_dispatch_width <= 16) {
/* Try a SIMD16 compile */
- nir_shader *nir16 = compile_cs_to_nir(compiler, mem_ctx, key,
+ nir_shader *nir16 = compile_cs_to_nir(compiler, mem_ctx, log_data, key,
src_shader, 16);
v16 = new fs_visitor(compiler, log_data, mem_ctx, key, &prog_data->base,
NULL, /* Never used in core profile */
@@ -7479,7 +7480,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data,
if (!fail_msg && (min_dispatch_width > 16 || (INTEL_DEBUG & DEBUG_DO32))) {
/* Try a SIMD32 compile */
- nir_shader *nir32 = compile_cs_to_nir(compiler, mem_ctx, key,
+ nir_shader *nir32 = compile_cs_to_nir(compiler, log_data, mem_ctx, key,
src_shader, 32);
v32 = new fs_visitor(compiler, log_data, mem_ctx, key, &prog_data->base,
NULL, /* Never used in core profile */
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index aa6788b9fe5..9c7877b920f 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -775,7 +775,7 @@ brw_nir_link_shaders(const struct brw_compiler *compiler,
*/
nir_shader *
brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
- bool is_scalar)
+ void *log_data, bool is_scalar)
{
const struct gen_device_info *devinfo = compiler->devinfo;
bool debug_enabled =
@@ -812,9 +812,17 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
nir_index_ssa_defs(function->impl);
}
- fprintf(stderr, "NIR (SSA form) for %s shader:\n",
+ char *buf;
+ size_t buf_size;
+ FILE * log_fp = open_memstream(&buf, &buf_size);
+ fprintf(log_fp, "NIR (SSA form) for %s shader:\n",
_mesa_shader_stage_to_string(nir->info.stage));
- nir_print_shader(nir, stderr);
+ nir_print_shader(nir, log_fp);
+ fclose(log_fp);
+ static GLuint msg_id = 0;
+ compiler->shader_debug_log(log_data, &msg_id, buf);
+ fputs(buf, stderr);
+ free(buf);
}
OPT(nir_convert_from_ssa, true);
@@ -837,9 +845,17 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
nir_sweep(nir);
if (unlikely(debug_enabled)) {
- fprintf(stderr, "NIR (final form) for %s shader:\n",
+ char *buf;
+ size_t buf_size;
+ FILE * log_fp = open_memstream(&buf, &buf_size);
+ fprintf(log_fp, "NIR (final form) for %s shader:\n",
_mesa_shader_stage_to_string(nir->info.stage));
- nir_print_shader(nir, stderr);
+ nir_print_shader(nir, log_fp);
+ fclose(log_fp);
+ static GLuint msg_id = 0;
+ compiler->shader_debug_log(log_data, &msg_id, buf);
+ fputs(buf, stderr);
+ free(buf);
}
return nir;
diff --git a/src/intel/compiler/brw_nir.h b/src/intel/compiler/brw_nir.h
index bc81950d47e..dda353a1665 100644
--- a/src/intel/compiler/brw_nir.h
+++ b/src/intel/compiler/brw_nir.h
@@ -123,6 +123,7 @@ bool brw_nir_lower_mem_access_bit_sizes(nir_shader *shader);
nir_shader *brw_postprocess_nir(nir_shader *nir,
const struct brw_compiler *compiler,
+ void *log_data,
bool is_scalar);
bool brw_nir_apply_attribute_workarounds(nir_shader *nir,
diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp
index b77bd798d17..598a84f365a 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -1204,7 +1204,7 @@ brw_compile_tes(const struct brw_compiler *compiler,
nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar);
brw_nir_lower_tes_inputs(nir, input_vue_map);
brw_nir_lower_vue_outputs(nir);
- nir = brw_postprocess_nir(nir, compiler, is_scalar);
+ nir = brw_postprocess_nir(nir, compiler, log_data, is_scalar);
brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
nir->info.outputs_written,
diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
index 6ed07b72f31..13a64e308bf 100644
--- a/src/intel/compiler/brw_vec4.cpp
+++ b/src/intel/compiler/brw_vec4.cpp
@@ -2857,7 +2857,7 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
brw_nir_lower_vs_inputs(shader, key->gl_attrib_wa_flags);
brw_nir_lower_vue_outputs(shader);
- shader = brw_postprocess_nir(shader, compiler, is_scalar);
+ shader = brw_postprocess_nir(shader, compiler, log_data, is_scalar);
prog_data->base.clip_distance_mask =
((1 << shader->info.clip_distance_array_size) - 1);
diff --git a/src/intel/compiler/brw_vec4_gs_visitor.cpp b/src/intel/compiler/brw_vec4_gs_visitor.cpp
index a6e38b0f379..db8bb298c81 100644
--- a/src/intel/compiler/brw_vec4_gs_visitor.cpp
+++ b/src/intel/compiler/brw_vec4_gs_visitor.cpp
@@ -642,7 +642,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
shader = brw_nir_apply_sampler_key(shader, compiler, &key->tex, is_scalar);
brw_nir_lower_vue_inputs(shader, &c.input_vue_map);
brw_nir_lower_vue_outputs(shader);
- shader = brw_postprocess_nir(shader, compiler, is_scalar);
+ shader = brw_postprocess_nir(shader, compiler, log_data, is_scalar);
prog_data->base.clip_distance_mask =
((1 << shader->info.clip_distance_array_size) - 1);
diff --git a/src/intel/compiler/brw_vec4_tcs.cpp b/src/intel/compiler/brw_vec4_tcs.cpp
index be0969dda12..2528088ce8c 100644
--- a/src/intel/compiler/brw_vec4_tcs.cpp
+++ b/src/intel/compiler/brw_vec4_tcs.cpp
@@ -404,7 +404,7 @@ brw_compile_tcs(const struct brw_compiler *compiler,
if (key->quads_workaround)
brw_nir_apply_tcs_quads_workaround(nir);
- nir = brw_postprocess_nir(nir, compiler, is_scalar);
+ nir = brw_postprocess_nir(nir, compiler, log_data, is_scalar);
if (is_scalar)
prog_data->instances = DIV_ROUND_UP(nir->info.tess.tcs_vertices_out, 8);
--
2.19.2
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