[Mesa-dev] [PATCH 13/59] intel/compiler: simplify f2*64 opcodes

Jason Ekstrand jason at jlekstrand.net
Fri Dec 7 15:39:22 UTC 2018


On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga <itoral at igalia.com> wrote:

> Now that this case only handles 64-bit destinations we can simplify
> a bit the code.
>

"the code a bit".  Sorry, English is hard....


> ---
>  src/intel/compiler/brw_fs_nir.cpp | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/intel/compiler/brw_fs_nir.cpp
> b/src/intel/compiler/brw_fs_nir.cpp
> index 6c765fc2661..3eba8a478f5 100644
> --- a/src/intel/compiler/brw_fs_nir.cpp
> +++ b/src/intel/compiler/brw_fs_nir.cpp
> @@ -833,7 +833,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld,
> nir_alu_instr *instr)
>         * 64-bit need to have the source data elements aligned to 64-bit.
>         * This restriction does not apply to BDW and later.
>         */
> -      if (type_sz(result.type) == 8 && type_sz(op[0].type) < 8 &&
> +      if (type_sz(op[0].type) < 8 &&
>            (devinfo->is_cherryview || gen_device_info_is_9lp(devinfo))) {
>           fs_reg tmp = bld.vgrf(result.type, 1);
>           tmp = subscript(tmp, op[0].type, 0);
> --
> 2.17.1
>
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