[Mesa-dev] [PATCH v2 3/3] i965/gen9: Add workarounds for object preemption.

[Kenneth Graunke]

On Thursday, December 13, 2018 5:00:43 PM PST Rafael Antognolli wrote:
> On Wed, Oct 31, 2018 at 04:27:31PM -0700, Kenneth Graunke wrote:
> > On Wednesday, October 31, 2018 11:15:28 AM PDT Rafael Antognolli wrote:
> > > On Tue, Oct 30, 2018 at 04:32:54PM -0700, Kenneth Graunke wrote:
> > > > On Monday, October 29, 2018 10:19:54 AM PDT Rafael Antognolli wrote:
> > > > Do we need any stalling when whacking CS_CHICKEN1...?
> > > 
> > > Hmmm... there's this:
> > > 
> > > "A fixed function pipe flush is required before modifying this field"
> > > 
> > > in the programming notes. I'm not sure what that is, but I assume it's
> > > some type of PIPE_CONTROL?
> > 
> > Yeah.  I'm not honestly sure what kind - "fixed function pipe flush"
> > isn't a thing.  Nobody ever uses wording that corresponds to actual
> > mechanics of the hardware. :(
> > 
> > Maybe this would work:
> > 
> >     brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH);
> 
> Hey Ken,
> 
> Ressurrecting this old thread... I just noticed that I had this in patch
> 2/3 (inside brw_enable_obj_preemption()):
> 
>  brw_emit_pipe_control_flush(brw, PIPE_CONTROL_FLUSH_ENABLE);
> 
> That's bit 7 of the PIPE_CONTROL, and from the docs:
> 
>  "Hardware on parsing PIPECONTROL command with Pipe Control Flush Enable
>  set will wait for all the outstanding post sync operations
>  corresponding to previously executed PIPECONTROL commands are complete
>  before making forward progress."
> 
> Do you think that's maybe what they meant? And in that case, I guess
> maybe I would need a PIPE_CONTROL with post sync operation right before
> this one, right?

I'm not sure.  A post-sync write immediate to the workaround buffer
followed by a pipe control flush enable sounds plausible.  My earlier
suggestion of render target flush as an end-of-pipe sync sounds
plausible as well.  I think what you sent in v3 is fine until we find
otherwise.
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