[Mesa-dev] [PATCH v2 1/3] st/glsl_to_tgsi: move nir detection earlier

Dieter N├╝tzel Dieter at nuetzel-hh.de
Fri Feb 2 08:26:40 UTC 2018


Hello Tim,

_this_ version brake UH, UV, mpv, blender 2.79 (some test files not 
all).
Must be something with the cache file(s).

export R600_DEBUG sisched,nir

UH and UV:
Start menu OK and then both:

Loading "core/properties/unigine.prop" 2 properties 0ms
Received signal SIGSEGV, invalid memory reference
AL lib: (EE) alc_cleanup: 1 device not closed

[1]    Fertig                        ./heaven

Loading "core/properties/unigine.prop" 2 properties 0ms
Received signal SIGSEGV, invalid memory reference
AL lib: (EE) alc_cleanup: 1 device not closed

[1]    Fertig                        ./valley

dmesg:
[62932.943040] [drm:amdgpu_ring_insert_nop [amdgpu]] *ERROR* amdgpu: 
writing more dwords to the ring than expected!
[62932.943093] [drm:amdgpu_ring_insert_nop [amdgpu]] *ERROR* amdgpu: 
writing more dwords to the ring than expected!
[62932.943146] [drm:amdgpu_ring_insert_nop [amdgpu]] *ERROR* amdgpu: 
writing more dwords to the ring than expected!

mpv:
mpv --hwdec vdpau /data/Filme/test.mkv
=> black, empty window but running

dmesg:
[64734.327722] [drm:uvd_v6_0_ring_emit_fence [amdgpu]] *ERROR* amdgpu: 
writing more dwords to the ring than expected!
[64734.327781] [drm:uvd_v6_0_ring_emit_fence [amdgpu]] *ERROR* amdgpu: 
writing more dwords to the ring than expected!
[64734.327808] [drm:uvd_v6_0_ring_emit_fence [amdgpu]] *ERROR* amdgpu: 
writing more dwords to the ring than expected!
[64734.327834] [drm:uvd_v6_0_ring_emit_fence [amdgpu]] *ERROR* amdgpu: 
writing more dwords to the ring than expected!

mplayer with some test file is OK.

Blender (2.79)
First run rendered some broken triangels etc. in OGL context,
then crash with the some demo files, but not with all.
Writing: /tmp/bh.crash.txt
Speicherschutzverletzung (core dumped)

# backtrace
blender(BLI_system_backtrace+0x33) [0x1382a43]
blender() [0x9a46a3]
/lib64/libc.so.6(+0x36150) [0x7ff196413150]
/usr/local/lib64/dri/radeonsi_dri.so(+0x3bc3a9) [0x7ff15df593a9]
/usr/local/lib64/dri/radeonsi_dri.so(+0x3bc4fb) [0x7ff15df594fb]
/usr/local/lib64/dri/radeonsi_dri.so(+0x3bdf14) [0x7ff15df5af14]
/usr/local/lib64/dri/radeonsi_dri.so(+0x27fc30) [0x7ff15de1cc30]
/usr/local/lib64/dri/radeonsi_dri.so(+0x2802ac) [0x7ff15de1d2ac]
/usr/local/lib64/dri/radeonsi_dri.so(+0x26a63f) [0x7ff15de0763f]
/usr/local/lib64/dri/radeonsi_dri.so(+0x28ad4e) [0x7ff15de27d4e]
/usr/local/lib64/dri/radeonsi_dri.so(+0x1b26dd) [0x7ff15dd4f6dd]
blender(GPU_shader_create_ex+0x3c8) [0xf95348]
blender(GPU_generate_pass+0xad2) [0xf99b12]
blender() [0xf8c989]
blender(GPU_material_from_blender+0x181) [0xf92421]
blender(GPU_begin_object_materials+0x738) [0xf88fc8]
blender(draw_object+0x3a3f) [0xaba06f]
blender() [0xa82f48]
blender(view3d_main_region_draw+0x193) [0xa86f43]
blender(ED_region_do_draw+0x395) [0xc97fe5]
blender(wm_draw_update+0x3a5) [0x9a9b85]
blender(WM_main+0x28) [0x9a5358]
blender(main+0x394) [0x987f64]
/lib64/libc.so.6(__libc_start_main+0xea) [0x7ff1963fdf4a]
blender(_start+0x2a) [0x9a13aa]

export R600_DEBUG sisched

mpv --hwdec vdpau /data/Filme/test.mkv
Using hardware decoding (vdpau).
VO: [opengl] 1920x1080 vdpau[yuv420p]
Speicherschutzverletzung (core dumped)

But then wiping the cache files solve it.

Apart from this (with disabled NIR, for now) SPEED was never ever 
GREATER!

Need badly some sleep...

Thanks.
Dieter


Am 02.02.2018 07:08, schrieb Timothy Arceri:
> We move the nir check before the shader cache call so that we can
> call a nir based caching function in a following patch.
> 
> Also with this change we simply check if vertex shaders support
> NIR rather than looping over the stages as mixing of shader types
> is not supported anyway.
> ---
>  src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 15 +++++++--------
>  1 file changed, 7 insertions(+), 8 deletions(-)
> 
> diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> index 84ed614927..355ba28218 100644
> --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> @@ -6916,15 +6916,20 @@ extern "C" {
>  GLboolean
>  st_link_shader(struct gl_context *ctx, struct gl_shader_program *prog)
>  {
> +   struct pipe_screen *pscreen = ctx->st->pipe->screen;
> +
> +   enum pipe_shader_ir preferred_ir = (enum pipe_shader_ir)
> +      pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX,
> +                                PIPE_SHADER_CAP_PREFERRED_IR);
> +   bool use_nir = preferred_ir == PIPE_SHADER_IR_NIR;
> +
>     /* Return early if we are loading the shader from on-disk cache */
>     if (st_load_tgsi_from_disk_cache(ctx, prog)) {
>        return GL_TRUE;
>     }
> 
> -   struct pipe_screen *pscreen = ctx->st->pipe->screen;
>     assert(prog->data->LinkStatus);
> 
> -   bool use_nir = false;
>     for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
>        if (prog->_LinkedShaders[i] == NULL)
>           continue;
> @@ -6944,12 +6949,6 @@ st_link_shader(struct gl_context *ctx, struct
> gl_shader_program *prog)
>        unsigned if_threshold = pscreen->get_shader_param(pscreen, 
> ptarget,
> 
> PIPE_SHADER_CAP_LOWER_IF_THRESHOLD);
> 
> -      enum pipe_shader_ir preferred_ir = (enum pipe_shader_ir)
> -         pscreen->get_shader_param(pscreen, ptarget,
> -                                   PIPE_SHADER_CAP_PREFERRED_IR);
> -      if (preferred_ir == PIPE_SHADER_IR_NIR)
> -         use_nir = true;
> -
>        /* If there are forms of indirect addressing that the driver
>         * cannot handle, perform the lowering pass.
>         */


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