[Mesa-dev] [PATCH 4/7] gallium/radeon: add 32-bit address space heaps

Marek Olšák maraeo at gmail.com
Fri Feb 2 20:48:50 UTC 2018


From: Marek Olšák <marek.olsak at amd.com>

Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
---
 src/gallium/drivers/radeon/radeon_winsys.h | 47 ++++++++++++++++++++++++++++--
 1 file changed, 44 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index 238c921..0a56539 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -46,20 +46,21 @@ enum radeon_bo_domain { /* bitfield */
     RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
 };
 
 enum radeon_bo_flag { /* bitfield */
     RADEON_FLAG_GTT_WC =        (1 << 0),
     RADEON_FLAG_NO_CPU_ACCESS = (1 << 1),
     RADEON_FLAG_NO_SUBALLOC =   (1 << 2),
     RADEON_FLAG_SPARSE =        (1 << 3),
     RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 4),
     RADEON_FLAG_READ_ONLY =     (1 << 5),
+    RADEON_FLAG_32BIT =    (1 << 6),
 };
 
 enum radeon_bo_usage { /* bitfield */
     RADEON_USAGE_READ = 2,
     RADEON_USAGE_WRITE = 4,
     RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE,
 
     /* The winsys ensures that the CS submission will be scheduled after
      * previously flushed CSs referencing this BO in a conflicting way.
      */
@@ -665,37 +666,45 @@ static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 				     const uint32_t *values, unsigned count)
 {
     memcpy(cs->current.buf + cs->current.cdw, values, count * 4);
     cs->current.cdw += count;
 }
 
 enum radeon_heap {
     RADEON_HEAP_VRAM_NO_CPU_ACCESS,
     RADEON_HEAP_VRAM_READ_ONLY,
+    RADEON_HEAP_VRAM_READ_ONLY_32BIT,
+    RADEON_HEAP_VRAM_32BIT,
     RADEON_HEAP_VRAM,
     RADEON_HEAP_GTT_WC,
     RADEON_HEAP_GTT_WC_READ_ONLY,
+    RADEON_HEAP_GTT_WC_READ_ONLY_32BIT,
+    RADEON_HEAP_GTT_WC_32BIT,
     RADEON_HEAP_GTT,
     RADEON_MAX_SLAB_HEAPS,
     RADEON_MAX_CACHED_HEAPS = RADEON_MAX_SLAB_HEAPS,
 };
 
 static inline enum radeon_bo_domain radeon_domain_from_heap(enum radeon_heap heap)
 {
     switch (heap) {
     case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
     case RADEON_HEAP_VRAM_READ_ONLY:
+    case RADEON_HEAP_VRAM_READ_ONLY_32BIT:
+    case RADEON_HEAP_VRAM_32BIT:
     case RADEON_HEAP_VRAM:
         return RADEON_DOMAIN_VRAM;
     case RADEON_HEAP_GTT_WC:
     case RADEON_HEAP_GTT_WC_READ_ONLY:
+    case RADEON_HEAP_GTT_WC_READ_ONLY_32BIT:
+    case RADEON_HEAP_GTT_WC_32BIT:
     case RADEON_HEAP_GTT:
         return RADEON_DOMAIN_GTT;
     default:
         assert(0);
         return (enum radeon_bo_domain)0;
     }
 }
 
 static inline unsigned radeon_flags_from_heap(enum radeon_heap heap)
 {
@@ -705,20 +714,31 @@ static inline unsigned radeon_flags_from_heap(enum radeon_heap heap)
     switch (heap) {
     case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
         return flags |
                RADEON_FLAG_NO_CPU_ACCESS;
 
     case RADEON_HEAP_VRAM_READ_ONLY:
     case RADEON_HEAP_GTT_WC_READ_ONLY:
         return flags |
                RADEON_FLAG_READ_ONLY;
 
+    case RADEON_HEAP_VRAM_READ_ONLY_32BIT:
+    case RADEON_HEAP_GTT_WC_READ_ONLY_32BIT:
+        return flags |
+               RADEON_FLAG_READ_ONLY |
+               RADEON_FLAG_32BIT;
+
+    case RADEON_HEAP_VRAM_32BIT:
+    case RADEON_HEAP_GTT_WC_32BIT:
+        return flags |
+               RADEON_FLAG_32BIT;
+
     case RADEON_HEAP_VRAM:
     case RADEON_HEAP_GTT_WC:
     case RADEON_HEAP_GTT:
     default:
         return flags;
     }
 }
 
 /* Return the heap index for winsys allocators, or -1 on failure. */
 static inline int radeon_get_heap_index(enum radeon_bo_domain domain,
@@ -730,46 +750,67 @@ static inline int radeon_get_heap_index(enum radeon_bo_domain domain,
     assert(!(flags & RADEON_FLAG_NO_CPU_ACCESS) || domain == RADEON_DOMAIN_VRAM);
 
     /* Resources with interprocess sharing don't use any winsys allocators. */
     if (!(flags & RADEON_FLAG_NO_INTERPROCESS_SHARING))
         return -1;
 
     /* Unsupported flags: NO_SUBALLOC, SPARSE. */
     if (flags & ~(RADEON_FLAG_GTT_WC |
                   RADEON_FLAG_NO_CPU_ACCESS |
                   RADEON_FLAG_NO_INTERPROCESS_SHARING |
-                  RADEON_FLAG_READ_ONLY))
+                  RADEON_FLAG_READ_ONLY |
+                  RADEON_FLAG_32BIT))
         return -1;
 
     switch (domain) {
     case RADEON_DOMAIN_VRAM:
-        switch (flags & (RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_READ_ONLY)) {
+        switch (flags & (RADEON_FLAG_NO_CPU_ACCESS |
+                         RADEON_FLAG_READ_ONLY |
+                         RADEON_FLAG_32BIT)) {
+        case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
         case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_READ_ONLY:
             assert(!"NO_CPU_ACCESS | READ_ONLY doesn't make sense");
             return -1;
+        case RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_32BIT:
+            assert(!"NO_CPU_ACCESS with 32BIT is disallowed");
+            return -1;
         case RADEON_FLAG_NO_CPU_ACCESS:
             return RADEON_HEAP_VRAM_NO_CPU_ACCESS;
+        case RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
+            return RADEON_HEAP_VRAM_READ_ONLY_32BIT;
         case RADEON_FLAG_READ_ONLY:
             return RADEON_HEAP_VRAM_READ_ONLY;
+        case RADEON_FLAG_32BIT:
+            return RADEON_HEAP_VRAM_32BIT;
         case 0:
             return RADEON_HEAP_VRAM;
         }
         break;
     case RADEON_DOMAIN_GTT:
-        switch (flags & (RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY)) {
+        switch (flags & (RADEON_FLAG_GTT_WC |
+                         RADEON_FLAG_READ_ONLY |
+                         RADEON_FLAG_32BIT)) {
+        case RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
+            return RADEON_HEAP_GTT_WC_READ_ONLY_32BIT;
         case RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY:
             return RADEON_HEAP_GTT_WC_READ_ONLY;
+        case RADEON_FLAG_GTT_WC | RADEON_FLAG_32BIT:
+            return RADEON_HEAP_GTT_WC_32BIT;
         case RADEON_FLAG_GTT_WC:
             return RADEON_HEAP_GTT_WC;
+        case RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
         case RADEON_FLAG_READ_ONLY:
             assert(!"READ_ONLY without WC is disallowed");
             return -1;
+        case RADEON_FLAG_32BIT:
+            assert(!"32BIT without WC is disallowed");
+            return -1;
         case 0:
             return RADEON_HEAP_GTT;
         }
         break;
     default:
         break;
     }
     return -1;
 }
 
-- 
2.7.4



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