[Mesa-dev] [PATCH v2 1/3] st/glsl_to_tgsi: move nir detection earlier - bisected
Dieter Nützel
Dieter at nuetzel-hh.de
Mon Feb 5 04:04:57 UTC 2018
Am 02.02.2018 10:24, schrieb Timothy Arceri:
> On 02/02/18 19:26, Dieter Nützel wrote:
>> Hello Tim,
>>
>> _this_ version brake UH, UV, mpv, blender 2.79 (some test files not
>> all).
>> Must be something with the cache file(s).
>
> The cache currently needs to be deleted when switching between nir and
> tgsi. I'm not sure it I should try to avoid this or not ... I guess it
> will probably save some bug reports so I'll try send a follow up
> patch.
Hi Tim,
it is NOT your fault.
I tracked it down to Marek's commit commit
be973ed21f6e456ebd753f26a99151d9ea6e765c
/opt/mesa> git bisect bad
be973ed21f6e456ebd753f26a99151d9ea6e765c is the first bad commit
commit be973ed21f6e456ebd753f26a99151d9ea6e765c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Jan 30 18:34:25 2018 +0100
radeonsi: load the right number of components for VS inputs and TBOs
The supported counts are 1, 2, 4. (3=4)
The following snippet loads float, vec2, vec3, and vec4:
Before:
buffer_load_format_x v9, v4, s[0:3], 0 idxen ; E0002000
80000904
buffer_load_format_xyzw v[0:3], v5, s[8:11], 0 idxen ; E00C2000
80020005
s_waitcnt vmcnt(0) ; BF8C0F70
buffer_load_format_xyzw v[2:5], v6, s[12:15], 0 idxen ; E00C2000
80030206
s_waitcnt vmcnt(0) ; BF8C0F70
buffer_load_format_xyzw v[5:8], v7, s[4:7], 0 idxen ; E00C2000
80010507
After:
buffer_load_format_x v10, v4, s[0:3], 0 idxen ; E0002000
80000A04
buffer_load_format_xy v[8:9], v5, s[8:11], 0 idxen ; E0042000
80020805
buffer_load_format_xyzw v[0:3], v6, s[12:15], 0 idxen ; E00C2000
80030006
s_waitcnt vmcnt(0) ; BF8C0F70
buffer_load_format_xyzw v[3:6], v7, s[4:7], 0 idxen ; E00C2000
80010307
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
:040000 040000 262b88d9e9f462b32595d6f15eddc0c6be4b997d
cf45e1bd87a8a0e12553f6476d51a750e114ea10 M src
But can't revert it clean for the time being.
Another week, another night,...
Cheers,
Dieter
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