[Mesa-dev] [PATCH 9/9] r600: work out target mask at framebuffer bind.

[Roland Scheidegger]

For 7-9/9
Reviewed-by: Roland Scheidegger <sroland at vmware.com>

Am 05.02.2018 um 05:29 schrieb Dave Airlie:
> From: Dave Airlie <airlied at redhat.com>
> 
> If we only get 1,2,3,6 framebuffers we want a sparse target mask.
> 
> Signed-off-by: Dave Airlie <airlied at redhat.com>
> ---
>  src/gallium/drivers/r600/evergreen_state.c | 10 +++++++---
>  src/gallium/drivers/r600/r600_pipe.h       |  1 +
>  src/gallium/drivers/r600/r600_state.c      |  2 +-
>  3 files changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
> index f8042c21c0..4c9163c2a7 100644
> --- a/src/gallium/drivers/r600/evergreen_state.c
> +++ b/src/gallium/drivers/r600/evergreen_state.c
> @@ -1436,7 +1436,7 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
>  	struct r600_surface *surf;
>  	struct r600_texture *rtex;
>  	uint32_t i, log_samples;
> -
> +	uint32_t target_mask = 0;
>  	/* Flush TC when changing the framebuffer state, because the only
>  	 * client not using TC that can change textures is the framebuffer.
>  	 * Other places don't typically have to flush TC.
> @@ -1463,6 +1463,8 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
>  		if (!surf)
>  			continue;
>  
> +		target_mask |= (0xf << (i * 4));
> +
>  		rtex = (struct r600_texture*)surf->base.texture;
>  
>  		r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
> @@ -1528,7 +1530,9 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
>  		r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
>  	}
>  
> -	if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
> +	if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs ||
> +	    rctx->cb_misc_state.bound_cbufs_target_mask != target_mask) {
> +		rctx->cb_misc_state.bound_cbufs_target_mask = target_mask;
>  		rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
>  		r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
>  	}
> @@ -2025,7 +2029,7 @@ static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_
>  {
>  	struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
>  	struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
> -	unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
> +	unsigned fb_colormask = a->bound_cbufs_target_mask;
>  	unsigned ps_colormask = a->ps_color_export_mask;
>  	unsigned rat_colormask = evergreen_construct_rat_mask(rctx, a, a->nr_cbufs);
>  	radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
> diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
> index 9b94f3654c..9caf3b8512 100644
> --- a/src/gallium/drivers/r600/r600_pipe.h
> +++ b/src/gallium/drivers/r600/r600_pipe.h
> @@ -152,6 +152,7 @@ struct r600_cb_misc_state {
>  	unsigned cb_color_control; /* this comes from blend state */
>  	unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
>  	unsigned nr_cbufs;
> +	unsigned bound_cbufs_target_mask;
>  	unsigned nr_ps_color_outputs;
>  	unsigned ps_color_export_mask;
>  	unsigned image_rat_enabled_mask;
> diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
> index 6ff8037d9c..5cf99c18b6 100644
> --- a/src/gallium/drivers/r600/r600_state.c
> +++ b/src/gallium/drivers/r600/r600_state.c
> @@ -1525,7 +1525,7 @@ static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom
>  		}
>  		radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
>  	} else {
> -		unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
> +		unsigned fb_colormask = a->bound_cbufs_target_mask;
>  		unsigned ps_colormask = a->ps_color_export_mask;
>  		unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
>  
>