[Mesa-dev] [PATCH] i965/tiled_memcpy: ytiled_to_linear a cache line at a time

Scott D Phillips scott.d.phillips at intel.com
Thu Feb 8 00:16:34 UTC 2018

Chris Wilson <chris at chris-wilson.co.uk> writes:

> From: Scott D Phillips <scott.d.phillips at intel.com>
> Similar to the transformation applied to linear_to_ytiled, also align
> each readback from the ytiled source to a cacheline (i.e. transfer a
> whole cacheline from the source before moving on to the next column).
> This will allow us to utilize movntqda (_mm_stream_si128) in a
> subsequent patch to obtain near WB readback performance when accessing
> the uncached ytiled memory, an order of magnitude improvement.

lgtm, or R-b if you want to take the authorship.

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