[Mesa-dev] [PATCH 1.5/16] intel/genxml/icl: Add Cache Mode SubSlice Register to gen11.xml

[Anuj Phogat]

Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
---
This patch will be squashed with [PATCH 01/16]

 src/intel/genxml/gen11.xml | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index 2490b0e25b..84020f7015 100644
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -3784,4 +3784,16 @@
     <field name="Color Compression Disable Mask" start="31" end="31" type="bool"/>
   </register>
 
+  <register name="CACHE_MODE_SS" length="1" num="0x0e420">
+    <field name="Instruction Level 1 Cache Disable" start="0" end="0" type="bool"/>
+    <field name="Instruction Level 1 Cache and In-Flight Queue Disable " start="1" end="1" type="bool"/>
+    <field name="Float Blend Optimization Enable" start="4" end="4" type="bool"/>
+    <field name="Per Sample Blend Opt Disable"  start="11" end="11" type="bool"/>
+
+    <field name="Instruction Level 1 Cache Disable Mask" start="16" end="16" type="bool"/>
+    <field name="Instruction Level 1 Cache and In-Flight Queue Disable Mask" start="17" end="17" type="bool"/>
+    <field name="Float Blend Optimization Enable Mask" start="20" end="20" type="bool"/>
+    <field name="Per Sample Blend Opt Disable Mask"  start="27" end="27" type="bool"/>
+  </register>
+
 </genxml>
-- 
2.13.6