[Mesa-dev] [PATCH v2] radv: compact varyings after removing unused ones

[Timothy Arceri]

On 16/02/18 21:07, Samuel Pitoiset wrote:
> Vega stats should be:
> 
> Totals from affected shaders:
> SGPRS: 106088 -> 106232 (0.14 %)
> VGPRS: 74652 -> 74700 (0.06 %)
> Spilled SGPRs: 692 -> 658 (-4.91 %)
> Code Size: 2967708 -> 2953028 (-0.49 %) bytes
> Max Waves: 18178 -> 18162 (-0.09 %)
> 
> My local override family was wrong because I have plugged my polaris10 
> yesterday. :)
> 
> On 02/16/2018 10:28 AM, Samuel Pitoiset wrote:
>> It makes no sense to compact before, and the description of
>> nir_compact_varyings() confirms that.
>>
>> Polaris10:
>> Totals from affected shaders:
>> SGPRS: 108528 -> 108128 (-0.37 %)
>> VGPRS: 74548 -> 74500 (-0.06 %)
>> Spilled SGPRs: 844 -> 814 (-3.55 %)
>> Code Size: 3007328 -> 2992932 (-0.48 %) bytes
>> Max Waves: 16019 -> 16009 (-0.06 %)
>>
>> Totals from affected shaders:
>> Vega10:
>> SGPRS: 108528 -> 108128 (-0.37 %)
>> VGPRS: 74548 -> 74500 (-0.06 %)
>> Spilled SGPRs: 844 -> 814 (-3.55 %)
>> Code Size: 3007328 -> 2992932 (-0.48 %) bytes
>> Max Waves: 16019 -> 16009 (-0.06 %)
>>
>> v2: - compact varyings even if no varyings were removed
>>      - update shader stats (which are better than v1)

Yeah that makes sense :)

Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>

>>
>> Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
>> ---
>>   src/amd/vulkan/radv_pipeline.c | 9 +++------
>>   1 file changed, 3 insertions(+), 6 deletions(-)
>>
>> diff --git a/src/amd/vulkan/radv_pipeline.c 
>> b/src/amd/vulkan/radv_pipeline.c
>> index 0d1958fc93..88646fda2f 100644
>> --- a/src/amd/vulkan/radv_pipeline.c
>> +++ b/src/amd/vulkan/radv_pipeline.c
>> @@ -1524,6 +1524,9 @@ radv_link_shaders(struct radv_pipeline 
>> *pipeline, nir_shader **shaders)
>>           bool progress = nir_remove_unused_varyings(ordered_shaders[i],
>>                                  ordered_shaders[i - 1]);
>> +        nir_compact_varyings(ordered_shaders[i],
>> +                     ordered_shaders[i - 1], true);
>> +
>>           if (progress) {
>>               if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
>>                   radv_lower_indirect_derefs(ordered_shaders[i],
>> @@ -1722,7 +1725,6 @@ void radv_create_shaders(struct radv_pipeline 
>> *pipeline,
>>           last = i;
>>       }
>> -    int prev = -1;
>>       for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
>>           const VkPipelineShaderStageCreateInfo *stage = pStages[i];
>> @@ -1753,11 +1755,6 @@ void radv_create_shaders(struct radv_pipeline 
>> *pipeline,
>>               nir_lower_io_to_scalar_early(nir[i], mask);
>>               radv_optimize_nir(nir[i]);
>>           }
>> -
>> -        if (prev != -1) {
>> -            nir_compact_varyings(nir[prev], nir[i], true);
>> -        }
>> -        prev = i;
>>       }
>>       if (nir[MESA_SHADER_TESS_CTRL]) {
>>
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