[Mesa-dev] [PATCH 08/14] radv: pass num_patches to tes from tcs

[Dave Airlie]

From: Dave Airlie <airlied at redhat.com>

TES needs num_patches to do some of the calculations.

Signed-off-by: Dave Airlie <airlied at redhat.com>
---
 src/amd/common/ac_nir_to_llvm.c | 4 +++-
 src/amd/common/ac_nir_to_llvm.h | 3 ++-
 src/amd/vulkan/radv_pipeline.c  | 4 ++++
 3 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 90b27603266..981c5d542a4 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2804,7 +2804,7 @@ static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
 		else
 			param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
 	} else {
-		LLVMValueRef num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
+		LLVMValueRef num_patches = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
 		LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
 		if (vertex_index)
 			param_stride = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
@@ -6956,6 +6956,7 @@ LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
 			ctx.abi.load_tess_coord = load_tess_coord;
 			ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
 			ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
+			ctx.tcs_num_patches = ctx.options->key.tes.num_patches;
 		} else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
 			if (shader_info->info.vs.needs_instance_id) {
 				if (ctx.options->key.vs.as_ls) {
@@ -7021,6 +7022,7 @@ LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
 		} else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
 			shader_info->tcs.outputs_written = ctx.tess_outputs_written;
 			shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
+			shader_info->tcs.num_patches = ctx.tcs_num_patches;
 			assert(ctx.tess_outputs_written == ctx.shader_info->info.tcs.outputs_written);
 			assert(ctx.tess_patch_outputs_written == ctx.shader_info->info.tcs.patch_outputs_written);
 		} else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h
index d81123144df..f1348c849b2 100644
--- a/src/amd/common/ac_nir_to_llvm.h
+++ b/src/amd/common/ac_nir_to_llvm.h
@@ -49,6 +49,7 @@ struct ac_vs_variant_key {
 struct ac_tes_variant_key {
 	uint32_t as_es:1;
 	uint32_t export_prim_id:1;
+	uint32_t num_patches;
 };
 
 struct ac_tcs_variant_key {
@@ -201,7 +202,7 @@ struct ac_shader_variant_info {
 			uint64_t outputs_written;
 			/* Which patch outputs are actually written */
 			uint32_t patch_outputs_written;
-
+			uint32_t num_patches;
 		} tcs;
 		struct {
 			struct ac_vs_output_info outinfo;
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 06b2db8455f..92a8d8c7051 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1786,6 +1786,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
 			                                                                      &code_sizes[MESA_SHADER_TESS_CTRL]);
 		}
 		modules[MESA_SHADER_VERTEX] = NULL;
+		keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
 	}
 
 	if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
@@ -1805,6 +1806,9 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
 			if (i == MESA_SHADER_TESS_CTRL) {
 				keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.ls_outputs_written);
 			}
+			if (i == MESA_SHADER_TESS_EVAL) {
+				keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
+			}
 			pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1,
 									  pipeline->layout,
 									  keys + i, &codes[i],
-- 
2.14.3