[Mesa-dev] [PATCH 05/21] intel/isl: Use a 4D physical total extent for size calculations
Jason Ekstrand
jason at jlekstrand.net
Fri Feb 23 07:06:45 UTC 2018
With Yf and Ys tiling, everything is actually four dimensional because
we can have multiple depth or multisampled array slices in the same
tile. This commit just enhances the calculations so they can handle it.
---
src/intel/isl/isl.c | 71 +++++++++++++++++++++++++++++++++++++++--------------
1 file changed, 53 insertions(+), 18 deletions(-)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 5bdc726..46aff46 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -988,7 +988,7 @@ isl_calc_phys_total_extent_el_gen4_2d(
const struct isl_extent4d *phys_level0_sa,
enum isl_array_pitch_span array_pitch_span,
uint32_t *array_pitch_el_rows,
- struct isl_extent2d *total_extent_el)
+ struct isl_extent4d *phys_total_el)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
@@ -1001,10 +1001,12 @@ isl_calc_phys_total_extent_el_gen4_2d(
image_align_sa, phys_level0_sa,
array_pitch_span,
&phys_slice0_sa);
- *total_extent_el = (struct isl_extent2d) {
+ *phys_total_el = (struct isl_extent4d) {
.w = isl_assert_div(phys_slice0_sa.w, fmtl->bw),
.h = *array_pitch_el_rows * (phys_level0_sa->array_len - 1) +
isl_assert_div(phys_slice0_sa.h, fmtl->bh),
+ .d = 1,
+ .a = 1,
};
}
@@ -1019,7 +1021,7 @@ isl_calc_phys_total_extent_el_gen4_3d(
const struct isl_extent3d *image_align_sa,
const struct isl_extent4d *phys_level0_sa,
uint32_t *array_pitch_el_rows,
- struct isl_extent2d *phys_total_el)
+ struct isl_extent4d *phys_total_el)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
@@ -1066,9 +1068,11 @@ isl_calc_phys_total_extent_el_gen4_3d(
*/
*array_pitch_el_rows =
isl_align_npot(phys_level0_sa->h, image_align_sa->h) / fmtl->bw;
- *phys_total_el = (struct isl_extent2d) {
+ *phys_total_el = (struct isl_extent4d) {
.w = isl_assert_div(total_w, fmtl->bw),
.h = isl_assert_div(total_h, fmtl->bh),
+ .d = 1,
+ .a = 1,
};
}
@@ -1084,7 +1088,7 @@ isl_calc_phys_total_extent_el_gen6_stencil_hiz(
const struct isl_extent3d *image_align_sa,
const struct isl_extent4d *phys_level0_sa,
uint32_t *array_pitch_el_rows,
- struct isl_extent2d *phys_total_el)
+ struct isl_extent4d *phys_total_el)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
@@ -1127,9 +1131,11 @@ isl_calc_phys_total_extent_el_gen6_stencil_hiz(
*array_pitch_el_rows =
isl_assert_div(isl_align(H0, image_align_sa->h), fmtl->bh);
- *phys_total_el = (struct isl_extent2d) {
+ *phys_total_el = (struct isl_extent4d) {
.w = isl_assert_div(MAX(total_top_w, total_bottom_w), fmtl->bw),
.h = isl_assert_div(total_h, fmtl->bh),
+ .d = 1,
+ .a = 1,
};
}
@@ -1144,7 +1150,7 @@ isl_calc_phys_total_extent_el_gen9_1d(
const struct isl_extent3d *image_align_sa,
const struct isl_extent4d *phys_level0_sa,
uint32_t *array_pitch_el_rows,
- struct isl_extent2d *phys_total_el)
+ struct isl_extent4d *phys_total_el)
{
MAYBE_UNUSED const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
@@ -1164,9 +1170,11 @@ isl_calc_phys_total_extent_el_gen9_1d(
}
*array_pitch_el_rows = 1;
- *phys_total_el = (struct isl_extent2d) {
+ *phys_total_el = (struct isl_extent4d) {
.w = isl_assert_div(slice_w, fmtl->bw),
.h = phys_level0_sa->array_len,
+ .d = 1,
+ .a = 1,
};
}
@@ -1184,7 +1192,7 @@ isl_calc_phys_total_extent_el(const struct isl_device *dev,
const struct isl_extent4d *phys_level0_sa,
enum isl_array_pitch_span array_pitch_span,
uint32_t *array_pitch_el_rows,
- struct isl_extent2d *total_extent_el)
+ struct isl_extent4d *phys_total_el)
{
switch (dim_layout) {
case ISL_DIM_LAYOUT_GEN9_1D:
@@ -1192,14 +1200,14 @@ isl_calc_phys_total_extent_el(const struct isl_device *dev,
isl_calc_phys_total_extent_el_gen9_1d(dev, info,
image_align_sa, phys_level0_sa,
array_pitch_el_rows,
- total_extent_el);
+ phys_total_el);
return;
case ISL_DIM_LAYOUT_GEN4_2D:
isl_calc_phys_total_extent_el_gen4_2d(dev, info, tile_info, msaa_layout,
image_align_sa, phys_level0_sa,
array_pitch_span,
array_pitch_el_rows,
- total_extent_el);
+ phys_total_el);
return;
case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ:
assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT);
@@ -1207,14 +1215,14 @@ isl_calc_phys_total_extent_el(const struct isl_device *dev,
image_align_sa,
phys_level0_sa,
array_pitch_el_rows,
- total_extent_el);
+ phys_total_el);
return;
case ISL_DIM_LAYOUT_GEN4_3D:
assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT);
isl_calc_phys_total_extent_el_gen4_3d(dev, info,
image_align_sa, phys_level0_sa,
array_pitch_el_rows,
- total_extent_el);
+ phys_total_el);
return;
}
}
@@ -1257,7 +1265,7 @@ isl_calc_row_pitch_alignment(const struct isl_surf_init_info *surf_info,
static uint32_t
isl_calc_linear_min_row_pitch(const struct isl_device *dev,
const struct isl_surf_init_info *info,
- const struct isl_extent2d *phys_total_el,
+ const struct isl_extent4d *phys_total_el,
uint32_t alignment)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
@@ -1270,7 +1278,7 @@ static uint32_t
isl_calc_tiled_min_row_pitch(const struct isl_device *dev,
const struct isl_surf_init_info *surf_info,
const struct isl_tile_info *tile_info,
- const struct isl_extent2d *phys_total_el,
+ const struct isl_extent4d *phys_total_el,
uint32_t alignment)
{
const struct isl_format_layout *fmtl = isl_format_get_layout(surf_info->format);
@@ -1290,7 +1298,7 @@ static uint32_t
isl_calc_min_row_pitch(const struct isl_device *dev,
const struct isl_surf_init_info *surf_info,
const struct isl_tile_info *tile_info,
- const struct isl_extent2d *phys_total_el,
+ const struct isl_extent4d *phys_total_el,
uint32_t alignment)
{
if (tile_info->tiling == ISL_TILING_LINEAR) {
@@ -1323,7 +1331,7 @@ isl_calc_row_pitch(const struct isl_device *dev,
const struct isl_surf_init_info *surf_info,
const struct isl_tile_info *tile_info,
enum isl_dim_layout dim_layout,
- const struct isl_extent2d *phys_total_el,
+ const struct isl_extent4d *phys_total_el,
uint32_t *out_row_pitch)
{
uint32_t alignment =
@@ -1446,7 +1454,7 @@ isl_surf_init_s(const struct isl_device *dev,
isl_choose_array_pitch_span(dev, info, dim_layout, &phys_level0_sa);
uint32_t array_pitch_el_rows;
- struct isl_extent2d phys_total_el;
+ struct isl_extent4d phys_total_el;
isl_calc_phys_total_extent_el(dev, info, &tile_info,
dim_layout, msaa_layout,
&image_align_sa, &phys_level0_sa,
@@ -1461,6 +1469,9 @@ isl_surf_init_s(const struct isl_device *dev,
uint32_t base_alignment;
uint64_t size;
if (tiling == ISL_TILING_LINEAR) {
+ /* LINEAR tiling has no concept of intra-tile arrays */
+ assert(phys_total_el.d == 1 && phys_total_el.a == 1);
+
size = (uint64_t) row_pitch * phys_total_el.h;
/* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfaceBaseAddress:
@@ -1482,7 +1493,31 @@ isl_surf_init_s(const struct isl_device *dev,
}
base_alignment = isl_round_up_to_power_of_two(base_alignment);
} else {
+ /* Pitches must make sense with the tiling */
+ assert(row_pitch % tile_info.phys_extent_B.width == 0);
+ assert(array_pitch_el_rows % tile_info.logical_extent_el.d == 0);
+ assert(array_pitch_el_rows % tile_info.logical_extent_el.a == 0);
+
+ uint32_t array_slices;
+ if (phys_total_el.d > 1) {
+ assert(phys_total_el.a == 1);
+ array_slices = isl_align_div(phys_total_el.d,
+ tile_info.logical_extent_el.d);
+ } else if (phys_total_el.a > 1) {
+ assert(phys_total_el.d == 1);
+ array_slices = isl_align_div(phys_total_el.a,
+ tile_info.logical_extent_el.a);
+ } else {
+ assert(phys_total_el.d == 1 && phys_total_el.a == 1);
+ array_slices = 1;
+ }
+
+ uint32_t array_pitch_tl_rows =
+ array_pitch_el_rows / MAX2(tile_info.logical_extent_el.d,
+ tile_info.logical_extent_el.a);
+
const uint32_t total_h_tl =
+ (array_slices - 1) * array_pitch_tl_rows +
isl_align_div(phys_total_el.h, tile_info.logical_extent_el.height);
size = (uint64_t) total_h_tl * tile_info.phys_extent_B.height * row_pitch;
--
2.5.0.400.gff86faf
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