[Mesa-dev] [PATCH v5 00/14] VK_KHR_16bit_storage input/output support for gen8+

Jose Maria Casanova Crespo jmcasanova at igalia.com
Fri Feb 23 13:15:49 UTC 2018


This is a re-send with rebased V5 series with the implementation of
the storageInputOutput16 feature for VK_KHR_16bit_storage:

This serie including the related to SSBO/UBO/PushConstant
sent today is already available also at:


If patches 1-8 could be reviewed the implementation would pass CTS tests
and 9-14 are mainly taking advantage of the Half Precision render target
support avaliable since SKL and BSW/CHV.

Finally an updated overview of the patches:

Patches 1-5 implement 16-bit vertex attribute inputs support on
i965. These include changes on anv. This was needed because 16-bit
surface formats do implicit conversion to 32-bit. To workaround this,
we override the 16-bit surface format, and use 32-bit ones.

Patch 6 implements load input and load store between pipeline

Patch 7 implements 16-bit store output support for fragment
shaders on i965. This implementation uses a 16-bit -> 32-bit
conversion and takes advance of the output format conversion to
write with 16bit format. This general solution is needed for
generations that the lack for support of half precision render
targets for all (BDW) or some formats (BSW,CHV).

Patch 8 enables VK_KHR_16bit_storage input/outputs support as
previous patch enables FS outputs for gen8+

Patches 9-14  implement the Half Precision Render Target support
to avoid the 32-bit -> 16-bit bit conversions introduced in [7] that
can be used at Gen9+ and is in some cases for BSW/CHV.

Cc: Jason Ekstrand <jason.ekstrand at intel.com>
Cc: Topi Pohjolainen <topi.pohjolainen at intel.com>

Alejandro PiƱeiro (3):
  anv/pipeline: Use 32-bit surface formats for 16-bit formats
  anv/cmd_buffer: Add a padding to the vertex buffer
  i965/fs: Use half_precision data_format on 16-bit fb writes

Jose Maria Casanova Crespo (11):
  compiler: Mark when input/ouput attribute at VS uses 16-bit
  i965/compiler: includes 16-bit vertex input
  i965/fs: Unpack 16-bit from 32-bit components in VS load_input
  i965/fs: Support 16-bit types at load_input and store_output
  i965/fs: Enable Render Target Write for 16-bit outputs
  anv: Enable VK_KHR_16bit_storage for input/output
  i965/fs: Include support for SEND data_format bit for Render Targets
  i965/disasm: Show half-precision data_format on rt_writes
  i965/fs: Mark 16-bit outputs on FS store_output
  i965/fs: 16-bit source payloads always use 1 register
  i965/fs: Enable 16-bit render target write on SKL and CHV

 src/compiler/glsl_types.h                      |  15 +++
 src/compiler/nir/nir_gather_info.c             |  10 +-
 src/compiler/shader_info.h                     |   3 +
 src/intel/compiler/brw_compiler.h              |   1 +
 src/intel/compiler/brw_disasm.c                |   4 +
 src/intel/compiler/brw_eu.h                    |   6 +-
 src/intel/compiler/brw_eu_emit.c               |  25 +++-
 src/intel/compiler/brw_fs.cpp                  |   6 +-
 src/intel/compiler/brw_fs_copy_propagation.cpp |   4 +-
 src/intel/compiler/brw_fs_generator.cpp        |   3 +-
 src/intel/compiler/brw_fs_nir.cpp              | 180 ++++++++++++++++++++++---
 src/intel/compiler/brw_fs_surface_builder.cpp  |   3 +-
 src/intel/compiler/brw_fs_visitor.cpp          |   6 +
 src/intel/compiler/brw_inst.h                  |   1 +
 src/intel/compiler/brw_shader.h                |   7 +
 src/intel/compiler/brw_vec4.cpp                |   1 +
 src/intel/compiler/brw_vec4_generator.cpp      |   3 +-
 src/intel/vulkan/anv_device.c                  |  11 +-
 src/intel/vulkan/genX_cmd_buffer.c             |  20 ++-
 src/intel/vulkan/genX_pipeline.c               |  34 +++++
 20 files changed, 306 insertions(+), 37 deletions(-)


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