[Mesa-dev] [PATCH 13/17] intel/compiler: Lower flrp32 on Gen11+

[Kenneth Graunke]

On Tuesday, February 20, 2018 9:15:20 PM PST Matt Turner wrote:
> The LRP instruction is no more.
> ---
>  src/intel/compiler/brw_compiler.c       | 35 +++++++++++++++++++++------------
>  src/intel/compiler/brw_fs_builder.h     |  2 +-
>  src/intel/compiler/brw_fs_generator.cpp |  2 +-
>  src/intel/compiler/brw_vec4_builder.h   |  2 +-
>  src/intel/compiler/brw_vec4_visitor.cpp |  2 +-
>  5 files changed, 26 insertions(+), 17 deletions(-)

The documentation suggests emulating it with MAD and NF, similar to PLN,
but I think that's only necessary if we need additional precision, which
GL doesn't require.  It looks like that would be 4 MADs in SIMD16 vs.
add/mul/neg, so I think lowering is the right call here.

Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: This is a digitally signed message part.
URL: <https://lists.freedesktop.org/archives/mesa-dev/attachments/20180223/1eea8c57/attachment.sig>