[Mesa-dev] [PATCH 2/8] radeonsi: fix vertex buffer address computation with full 64-bit addresses

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

Cc: 18.0 <mesa-stable at lists.freedesktop.org>
---
 src/gallium/drivers/radeonsi/si_descriptors.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index a4dae44..89fb614 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -1118,23 +1118,23 @@ bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
 		unsigned vbo_index = velems->vertex_buffer_index[i];
 		uint32_t *desc = &ptr[i*4];
 
 		vb = &sctx->vertex_buffer[vbo_index];
 		rbuffer = (struct r600_resource*)vb->buffer.resource;
 		if (!rbuffer) {
 			memset(desc, 0, 16);
 			continue;
 		}
 
-		int offset = (int)vb->buffer_offset + (int)velems->src_offset[i];
-		int64_t va = (int64_t)rbuffer->gpu_address + offset;
-		assert(va > 0);
+		int64_t offset = (int64_t)((int)vb->buffer_offset) +
+				 velems->src_offset[i];
+		uint64_t va = rbuffer->gpu_address + offset;
 
 		int64_t num_records = (int64_t)rbuffer->b.b.width0 - offset;
 		if (sctx->b.chip_class != VI && vb->stride) {
 			/* Round up by rounding down and adding 1 */
 			num_records = (num_records - velems->format_size[i]) /
 				      vb->stride + 1;
 		}
 		assert(num_records >= 0 && num_records <= UINT_MAX);
 
 		desc[0] = va;
-- 
2.7.4