[Mesa-dev] [PATCH] radv: limit the scissor bug workaround to Vega 10 and Raven

[Bas Nieuwenhuizen]

Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>

On Thu, Jan 4, 2018 at 4:24 PM, Samuel Pitoiset
<samuel.pitoiset at gmail.com> wrote:
> Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
> ---
>  src/amd/vulkan/radv_cmd_buffer.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
> index 6dc80acef0..a6975097b9 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -1118,7 +1118,12 @@ radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
>  {
>         uint32_t count = cmd_buffer->state.dynamic.scissor.count;
>
> -       if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
> +       /* Vega10/Raven scissor bug workaround. This must be done before VPORT
> +        * scissor registers are changed. There is also a more efficient but
> +        * more involved alternative workaround.
> +        */
> +       if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA10 ||
> +           cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN) {
>                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
>                 si_emit_cache_flush(cmd_buffer);
>         }
> --
> 2.15.1
>
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