[Mesa-dev] [PATCH] ac: add load_patch_vertices_in() to the abi

[Samuel Pitoiset]

Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>

On 01/10/2018 07:28 AM, Timothy Arceri wrote:
> Fixes the follow test for radeonsi nir:
> 
> tests/spec/arb_tessellation_shader/execution/quads.shader_test
> 
> Also stops 8 other tests from crashing, they now just fail e.g.
> 
> tcs-output-array-float-index-rd-after-barrier.shader_test
> ---
>   src/amd/common/ac_nir_to_llvm.c          | 11 ++++++++++-
>   src/amd/common/ac_shader_abi.h           |  2 ++
>   src/gallium/drivers/radeonsi/si_shader.c | 20 ++++++++++++++------
>   3 files changed, 26 insertions(+), 7 deletions(-)
> 
> diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
> index 4d2c8f20ab..2023dd49c6 100644
> --- a/src/amd/common/ac_nir_to_llvm.c
> +++ b/src/amd/common/ac_nir_to_llvm.c
> @@ -4157,6 +4157,13 @@ load_tess_coord(struct ac_shader_abi *abi, LLVMTypeRef type,
>   	return LLVMBuildBitCast(ctx->builder, result, type, "");
>   }
>   
> +static LLVMValueRef
> +load_patch_vertices_in(struct ac_shader_abi *abi)
> +{
> +	struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
> +	return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
> +}
> +
>   static void visit_intrinsic(struct ac_nir_context *ctx,
>                               nir_intrinsic_instr *instr)
>   {
> @@ -4357,7 +4364,7 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
>   		result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
>   		break;
>   	case nir_intrinsic_load_patch_vertices_in:
> -		result = LLVMConstInt(ctx->ac.i32, ctx->nctx->options->key.tcs.input_vertices, false);
> +		result = ctx->abi->load_patch_vertices_in(ctx->abi);
>   		break;
>   	default:
>   		fprintf(stderr, "Unknown intrinsic: ");
> @@ -6688,11 +6695,13 @@ LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
>   			ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
>   			ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
>   			ctx.abi.load_tess_varyings = load_tcs_varyings;
> +			ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
>   			ctx.abi.store_tcs_outputs = store_tcs_output;
>   		} else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
>   			ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
>   			ctx.abi.load_tess_varyings = load_tes_input;
>   			ctx.abi.load_tess_coord = load_tess_coord;
> +			ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
>   		} else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
>   			if (shader_info->info.vs.needs_instance_id) {
>   				if (ctx.ac.chip_class == GFX9 &&
> diff --git a/src/amd/common/ac_shader_abi.h b/src/amd/common/ac_shader_abi.h
> index 6ed7dbb04e..3e9e7a4786 100644
> --- a/src/amd/common/ac_shader_abi.h
> +++ b/src/amd/common/ac_shader_abi.h
> @@ -104,6 +104,8 @@ struct ac_shader_abi {
>   					LLVMTypeRef type,
>   					unsigned num_components);
>   
> +	LLVMValueRef (*load_patch_vertices_in)(struct ac_shader_abi *abi);
> +
>   	LLVMValueRef (*load_tess_level)(struct ac_shader_abi *abi,
>   					unsigned varying_id);
>   
> diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
> index 2e74f4a33c..391ee04741 100644
> --- a/src/gallium/drivers/radeonsi/si_shader.c
> +++ b/src/gallium/drivers/radeonsi/si_shader.c
> @@ -1967,6 +1967,17 @@ static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
>   
>   }
>   
> +static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
> +{
> +	struct si_shader_context *ctx = si_shader_context_from_abi(abi);
> +	if (ctx->type == PIPE_SHADER_TESS_CTRL)
> +		return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 26, 6);
> +	else if (ctx->type == PIPE_SHADER_TESS_EVAL)
> +		return get_num_tcs_out_vertices(ctx);
> +	else
> +		assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
> +}
> +
>   void si_load_system_value(struct si_shader_context *ctx,
>   			  unsigned index,
>   			  const struct tgsi_full_declaration *decl)
> @@ -2075,12 +2086,7 @@ void si_load_system_value(struct si_shader_context *ctx,
>   		break;
>   
>   	case TGSI_SEMANTIC_VERTICESIN:
> -		if (ctx->type == PIPE_SHADER_TESS_CTRL)
> -			value = unpack_param(ctx, ctx->param_tcs_out_lds_layout, 26, 6);
> -		else if (ctx->type == PIPE_SHADER_TESS_EVAL)
> -			value = get_num_tcs_out_vertices(ctx);
> -		else
> -			assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
> +		value = si_load_patch_vertices_in(&ctx->abi);
>   		break;
>   
>   	case TGSI_SEMANTIC_TESSINNER:
> @@ -5998,6 +6004,7 @@ static bool si_compile_tgsi_main(struct si_shader_context *ctx,
>   		bld_base->emit_store = store_output_tcs;
>   		ctx->abi.store_tcs_outputs = si_nir_store_output_tcs;
>   		ctx->abi.emit_outputs = si_llvm_emit_tcs_epilogue;
> +		ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
>   		bld_base->emit_epilogue = si_tgsi_emit_epilogue;
>   		break;
>   	case PIPE_SHADER_TESS_EVAL:
> @@ -6005,6 +6012,7 @@ static bool si_compile_tgsi_main(struct si_shader_context *ctx,
>   		ctx->abi.load_tess_varyings = si_nir_load_input_tes;
>   		ctx->abi.load_tess_coord = si_load_tess_coord;
>   		ctx->abi.load_tess_level = si_load_tess_level;
> +		ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
>   		if (shader->key.as_es)
>   			ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
>   		else
>