[Mesa-dev] [PATCH v2 00/12] Use clear color address in surface state.

[Pohjolainen, Topi]

On Fri, Jan 19, 2018 at 11:54:35AM -0800, Rafael Antognolli wrote:
> Second version of this series, with (hopefully) full support for this in
> Vulkan.

I started reading this but realized quickly that Jason just altered
the way clear value and compression state are stored. I guess you'll
need to rebase a little? See: "anv/cmd_buffer: Rework aux tracking".

> 
> Rafael Antognolli (12):
>   anv/image: Do not override lower bits of dword.
>   genxml: Preserve fields that share dword space with addresses.
>   intel/genxml: Use a single field for clear color address on gen10.
>   intel/isl: Add support to emit clear value address.
>   anv: Make the clear address 64 bytes aligned.
>   intel/blorp: Add suport for fast clear address.
>   i965/miptree: Add space to store the clear value in the aux surface.
>   i965/blorp: Update the fast clear color entry buffer.
>   i965/surface_state: Emit the clear color address instead of value.
>   i965/surface_state: Silence warning.
>   anv: Emit the fast clear color address, instead of value.
>   anv: Use clear address for HiZ fast clears too.
> 
>  src/intel/blorp/blorp_genX_exec.h                | 12 +++-
>  src/intel/genxml/gen10.xml                       |  7 +--
>  src/intel/genxml/gen_pack_header.py              |  9 ++-
>  src/intel/isl/isl.h                              |  9 +++
>  src/intel/isl/isl_surface_state.c                | 18 ++++--
>  src/intel/vulkan/anv_device.c                    | 19 ++++++
>  src/intel/vulkan/anv_image.c                     | 52 +++++++++++++----
>  src/intel/vulkan/anv_private.h                   | 18 +++++-
>  src/intel/vulkan/genX_cmd_buffer.c               | 74 +++++++++++++++++++-----
>  src/mesa/drivers/dri/i965/brw_blorp.c            | 26 +++++++++
>  src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 18 +++++-
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c    | 11 ++++
>  12 files changed, 231 insertions(+), 42 deletions(-)
> 
> -- 
> 2.14.3
> 
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