[Mesa-dev] [PATCH v2 10/20] radv: Compute shader_z_format when emitting it.

[Bas Nieuwenhuizen]

---
 src/amd/vulkan/radv_pipeline.c | 10 +++-------
 src/amd/vulkan/radv_private.h  |  1 -
 2 files changed, 3 insertions(+), 8 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 75137c8629..84d889a7c4 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2830,7 +2830,9 @@ radv_pipeline_generate_fragment_shader(struct radeon_winsys_cs *cs,
 	radeon_set_context_reg(cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
 
 	radeon_set_context_reg(cs, R_028710_SPI_SHADER_Z_FORMAT,
-			       pipeline->graphics.shader_z_format);
+	                       ac_get_spi_shader_z_format(ps->info.fs.writes_z,
+	                                                  ps->info.fs.writes_stencil,
+	                                                  ps->info.fs.writes_sample_mask));
 
 	radeon_set_context_reg(cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
 
@@ -2994,12 +2996,6 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
 	if (pipeline->device->physical_device->has_rbplus)
 		pipeline->graphics.db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
 
-	unsigned shader_z_format =
-		ac_get_spi_shader_z_format(ps->info.fs.writes_z,
-					   ps->info.fs.writes_stencil,
-					   ps->info.fs.writes_sample_mask);
-	pipeline->graphics.shader_z_format = shader_z_format;
-
 	calculate_vgt_gs_mode(pipeline);
 
 	for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index b7f1f86dbf..8acf91c4ff 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1218,7 +1218,6 @@ struct radv_pipeline {
 			struct radv_tessellation_state tess;
 			struct radv_gs_state gs;
 			uint32_t db_shader_control;
-			uint32_t shader_z_format;
 			uint32_t spi_baryc_cntl;
 			unsigned prim;
 			unsigned gs_out;
-- 
2.16.1