[Mesa-dev] [PATCH 4/4] radv: repack some structures post pipeline rework.
Dave Airlie
airlied at gmail.com
Tue Jan 30 23:41:59 UTC 2018
From: Dave Airlie <airlied at redhat.com>
Bas's pipeline rework made me relook at the struct packing:
radv_cmd_state: 984->968
radv_cmd_buffer: 2910->2896
radv_image: 1008->1000
radv_pipeline: 1640->1632
Signed-off-by: Dave Airlie <airlied at redhat.com>
---
src/amd/vulkan/radv_private.h | 25 ++++++++++++++-----------
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index e856f5f9b07..46a2e02612e 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -886,12 +886,14 @@ struct radv_attachment_state {
struct radv_cmd_state {
/* Vertex descriptors */
+ enum radv_cmd_flush_bits flush_bits;
bool vb_prefetch_dirty;
+ bool push_descriptors_dirty;
+ bool predicating;
+
uint64_t vb_va;
unsigned vb_size;
- bool push_descriptors_dirty;
- bool predicating;
uint32_t dirty;
struct radv_pipeline * pipeline;
@@ -915,7 +917,6 @@ struct radv_cmd_state {
int32_t last_primitive_reset_en;
uint32_t last_primitive_reset_index;
- enum radv_cmd_flush_bits flush_bits;
unsigned active_occlusion_queries;
float offset_scale;
uint32_t descriptors_dirty;
@@ -962,14 +963,16 @@ struct radv_cmd_buffer {
VkCommandBufferUsageFlags usage_flags;
VkCommandBufferLevel level;
enum radv_cmd_buffer_status status;
+ uint32_t queue_family_index;
+ VkShaderStageFlags push_constant_stages;
+ VkResult record_result;
+
struct radeon_winsys_cs *cs;
struct radv_cmd_state state;
struct radv_vertex_binding vertex_bindings[MAX_VBS];
- uint32_t queue_family_index;
uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
- VkShaderStageFlags push_constant_stages;
struct radv_push_descriptor_set push_descriptors;
struct radv_descriptor_set meta_push_descriptors;
struct radv_descriptor_set *descriptors[MAX_SETS];
@@ -983,12 +986,11 @@ struct radv_cmd_buffer {
bool tess_rings_needed;
bool sample_positions_needed;
- VkResult record_result;
int ring_offsets_idx; /* just used for verification */
uint32_t gfx9_fence_offset;
- struct radeon_winsys_bo *gfx9_fence_bo;
uint32_t gfx9_fence_idx;
+ struct radeon_winsys_bo *gfx9_fence_bo;
};
struct radv_image;
@@ -1171,11 +1173,11 @@ struct radv_pipeline {
struct radv_pipeline_layout * layout;
+ VkShaderStageFlags active_stages;
bool needs_data_cache;
bool need_indirect_descriptor_sets;
struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
struct radv_shader_variant *gs_copy_shader;
- VkShaderStageFlags active_stages;
struct radeon_winsys_cs cs;
@@ -1189,13 +1191,13 @@ struct radv_pipeline {
struct radv_multisample_state ms;
uint32_t spi_baryc_cntl;
bool prim_restart_enable;
+ bool can_use_guardband;
+ uint8_t vtx_emit_num;
unsigned esgs_ring_size;
unsigned gsvs_ring_size;
uint32_t vtx_base_sgpr;
struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
- uint8_t vtx_emit_num;
struct radv_prim_vertex_count prim_vertex_count;
- bool can_use_guardband;
uint32_t needed_dynamic_state;
} graphics;
};
@@ -1301,13 +1303,14 @@ struct radv_image {
unsigned queue_family_mask;
bool exclusive;
bool shareable;
+ bool tc_compatible_htile;
/* Set when bound */
struct radeon_winsys_bo *bo;
VkDeviceSize offset;
uint64_t dcc_offset;
uint64_t htile_offset;
- bool tc_compatible_htile;
+
struct radeon_surf surface;
struct radv_fmask_info fmask;
--
2.14.3
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