[Mesa-dev] [PATCH] anv/icl: Don't set float blend optimization bit in CACHE_MODE_SS

[Lionel Landwerlin]

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>

On 03/07/18 21:24, Anuj Phogat wrote:
> Bump
> On Fri, Jun 1, 2018 at 2:40 PM Anuj Phogat <anuj.phogat at gmail.com> wrote:
>> CACHE_MODE_SS is not listed in gfxspecs table for user mode
>> non-privileged registers. So, making any changes from Mesa
>> will do nothing. Kernel is already setting this bit in
>> CACHE_MODE_SS register which is saved/restored to/from
>> the HW context image.
>>
>> Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
>> Cc: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
>> ---
>>   src/intel/vulkan/genX_state.c | 12 ------------
>>   1 file changed, 12 deletions(-)
>>
>> diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
>> index c6e54046910..06dc2d345e2 100644
>> --- a/src/intel/vulkan/genX_state.c
>> +++ b/src/intel/vulkan/genX_state.c
>> @@ -121,18 +121,6 @@ genX(init_device_state)(struct anv_device *device)
>>      }
>>   #endif
>>
>> -#if GEN_GEN == 10 || GEN_GEN == 11
>> -   uint32_t cache_mode_ss;
>> -   anv_pack_struct(&cache_mode_ss, GENX(CACHE_MODE_SS),
>> -                   .FloatBlendOptimizationEnable = true,
>> -                   .FloatBlendOptimizationEnableMask = true);
>> -
>> -   anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
>> -      lri.RegisterOffset = GENX(CACHE_MODE_SS_num);
>> -      lri.DataDWord      = cache_mode_ss;
>> -   }
>> -#endif
>> -
>>      anv_batch_emit(&batch, GENX(3DSTATE_AA_LINE_PARAMETERS), aa);
>>
>>      anv_batch_emit(&batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
>> --
>> 2.17.0
>>