[Mesa-dev] [PATCH 1/2] raddv: only flush DB meta in pipeline image barriers when needed
Bas Nieuwenhuizen
bas at basnieuwenhuizen.nl
Thu Jul 5 11:34:18 UTC 2018
If you fix the typo in the title, this patch is
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
On Thu, Jul 5, 2018 at 12:54 PM, Samuel Pitoiset
<samuel.pitoiset at gmail.com> wrote:
> If the given image doesn't have HTILE, that's useless to flush
> DB metadata.
>
> Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 22 +++++++++++++++-------
> 1 file changed, 15 insertions(+), 7 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
> index dccf36c807..3a017b5fef 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -1960,7 +1960,8 @@ static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
>
> static enum radv_cmd_flush_bits
> radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
> - VkAccessFlags src_flags)
> + VkAccessFlags src_flags,
> + struct radv_image *image)
> {
> enum radv_cmd_flush_bits flush_bits = 0;
> uint32_t b;
> @@ -1974,8 +1975,10 @@ radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
> RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
> break;
> case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
> - flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
> - RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
> + flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
> + if (!image || (image && radv_image_has_htile(image))) {
> + flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
> + }
> break;
> case VK_ACCESS_TRANSFER_WRITE_BIT:
> flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
> @@ -2034,7 +2037,8 @@ radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
>
> static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
> {
> - cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
> + cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
> + NULL);
> radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
> cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
> NULL);
> @@ -4196,20 +4200,24 @@ radv_barrier(struct radv_cmd_buffer *cmd_buffer,
> }
>
> for (uint32_t i = 0; i < memoryBarrierCount; i++) {
> - src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
> + src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
> + NULL);
> dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
> NULL);
> }
>
> for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
> - src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
> + src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
> + NULL);
> dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
> NULL);
> }
>
> for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
> RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
> - src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
> +
> + src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
> + image);
> dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
> image);
> }
> --
> 2.18.0
>
> _______________________________________________
> mesa-dev mailing list
> mesa-dev at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
More information about the mesa-dev
mailing list