[Mesa-dev] [PATCH 6/9] radeonsi: merge DCC/CMASK/HTILE priority flags
Marek Olšák
maraeo at gmail.com
Thu Jul 12 05:26:37 UTC 2018
From: Marek Olšák <marek.olsak at amd.com>
For a later simplification.
---
src/gallium/drivers/r600/evergreen_state.c | 4 ++--
src/gallium/drivers/r600/r600_state.c | 2 +-
src/gallium/drivers/radeon/radeon_winsys.h | 4 +---
src/gallium/drivers/radeonsi/si_debug.c | 4 +---
src/gallium/drivers/radeonsi/si_descriptors.c | 2 +-
src/gallium/drivers/radeonsi/si_state.c | 4 ++--
6 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 76a3e0e441a..57b82e7855f 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1857,21 +1857,21 @@ static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r
&rctx->b.gfx,
(struct r600_resource*)cb->base.texture,
RADEON_USAGE_READWRITE,
tex->resource.b.b.nr_samples > 1 ?
RADEON_PRIO_COLOR_BUFFER_MSAA :
RADEON_PRIO_COLOR_BUFFER);
if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
cmask_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
tex->cmask_buffer, RADEON_USAGE_READWRITE,
- RADEON_PRIO_CMASK);
+ RADEON_PRIO_SEPARATE_META);
} else {
cmask_reloc = reloc;
}
radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
@@ -2046,21 +2046,21 @@ static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom
if (a->rsurf && a->rsurf->db_htile_surface) {
struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
unsigned reloc_idx;
radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource,
- RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
+ RADEON_USAGE_READWRITE, RADEON_PRIO_SEPARATE_META);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, reloc_idx);
} else {
radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
}
}
static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
{
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index d241d27d1b9..9f3779f16d4 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1547,21 +1547,21 @@ static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom
struct r600_db_state *a = (struct r600_db_state*)atom;
if (a->rsurf && a->rsurf->db_htile_surface) {
struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
unsigned reloc_idx;
radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource,
- RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE);
+ RADEON_USAGE_READWRITE, RADEON_PRIO_SEPARATE_META);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, reloc_idx);
} else {
radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, 0);
}
}
static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
{
struct radeon_cmdbuf *cs = rctx->b.gfx.cs;
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index e9ae1f925c4..bcd6831ed35 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -145,23 +145,21 @@ enum radeon_bo_priority {
RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 32,
RADEON_PRIO_COLOR_BUFFER = 36,
RADEON_PRIO_DEPTH_BUFFER = 40,
RADEON_PRIO_COLOR_BUFFER_MSAA = 44,
RADEON_PRIO_DEPTH_BUFFER_MSAA = 48,
- RADEON_PRIO_CMASK = 52,
- RADEON_PRIO_DCC,
- RADEON_PRIO_HTILE,
+ RADEON_PRIO_SEPARATE_META = 52,
RADEON_PRIO_SHADER_BINARY, /* the hw can't hide instruction cache misses */
RADEON_PRIO_SHADER_RINGS = 56,
RADEON_PRIO_SCRATCH_BUFFER = 60,
/* 63 is the maximum value */
};
struct winsys_handle;
struct radeon_winsys_ctx;
diff --git a/src/gallium/drivers/radeonsi/si_debug.c b/src/gallium/drivers/radeonsi/si_debug.c
index 0e5012b9d32..50375ce7cbe 100644
--- a/src/gallium/drivers/radeonsi/si_debug.c
+++ b/src/gallium/drivers/radeonsi/si_debug.c
@@ -504,23 +504,21 @@ static const char *priority_to_string(enum radeon_bo_priority priority)
ITEM(VERTEX_BUFFER),
ITEM(SHADER_RW_BUFFER),
ITEM(COMPUTE_GLOBAL),
ITEM(SAMPLER_TEXTURE),
ITEM(SHADER_RW_IMAGE),
ITEM(SAMPLER_TEXTURE_MSAA),
ITEM(COLOR_BUFFER),
ITEM(DEPTH_BUFFER),
ITEM(COLOR_BUFFER_MSAA),
ITEM(DEPTH_BUFFER_MSAA),
- ITEM(CMASK),
- ITEM(DCC),
- ITEM(HTILE),
+ ITEM(SEPARATE_META),
ITEM(SHADER_BINARY),
ITEM(SHADER_RINGS),
ITEM(SCRATCH_BUFFER),
};
#undef ITEM
assert(priority < ARRAY_SIZE(table));
return table[priority];
}
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 83f62e4ac93..06e95e863eb 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -262,21 +262,21 @@ static void si_sampler_view_add_buffer(struct si_context *sctx,
priority = si_get_sampler_view_priority(&tex->buffer);
radeon_add_to_gfx_buffer_list_check_mem(sctx, &tex->buffer, usage, priority,
check_mem);
if (resource->target == PIPE_BUFFER)
return;
/* Add separate DCC. */
if (tex->dcc_separate_buffer) {
radeon_add_to_gfx_buffer_list_check_mem(sctx, tex->dcc_separate_buffer,
- usage, RADEON_PRIO_DCC, check_mem);
+ usage, RADEON_PRIO_SEPARATE_META, check_mem);
}
}
static void si_sampler_views_begin_new_cs(struct si_context *sctx,
struct si_samplers *samplers)
{
unsigned mask = samplers->enabled_mask;
/* Add buffers to the CS. */
while (mask) {
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index a51b3739f03..7bbb1f63280 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2990,28 +2990,28 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
tex = (struct si_texture *)cb->base.texture;
radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
&tex->buffer, RADEON_USAGE_READWRITE,
tex->buffer.b.b.nr_samples > 1 ?
RADEON_PRIO_COLOR_BUFFER_MSAA :
RADEON_PRIO_COLOR_BUFFER);
if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
tex->cmask_buffer, RADEON_USAGE_READWRITE,
- RADEON_PRIO_CMASK);
+ RADEON_PRIO_SEPARATE_META);
}
if (tex->dcc_separate_buffer)
radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
tex->dcc_separate_buffer,
RADEON_USAGE_READWRITE,
- RADEON_PRIO_DCC);
+ RADEON_PRIO_SEPARATE_META);
/* Compute mutable surface parameters. */
cb_color_base = tex->buffer.gpu_address >> 8;
cb_color_fmask = 0;
cb_color_cmask = tex->cmask_base_address_reg;
cb_dcc_base = 0;
cb_color_info = cb->cb_color_info | tex->cb_color_info;
cb_color_attrib = cb->cb_color_attrib;
if (cb->base.u.tex.level > 0)
--
2.17.1
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