[Mesa-dev] [PATCH 7/9] radeonsi: rework RADEON_PRIO flags to be <= 31

Marek Olšák maraeo at gmail.com
Thu Jul 12 20:51:59 UTC 2018


On Thu, Jul 12, 2018 at 2:24 AM, Timothy Arceri <tarceri at itsqueeze.com> wrote:
> Two suggestions below.
>
>
> On 12/07/18 15:26, Marek Olšák wrote:
>>
>> From: Marek Olšák <marek.olsak at amd.com>
>>
>> This decreases sizeof(struct amdgpu_cs_buffer) from 24 to 16 bytes.
>> ---
>>   src/gallium/drivers/radeon/radeon_winsys.h    | 39 ++++++++++---------
>>   src/gallium/drivers/radeonsi/si_debug.c       |  2 +-
>>   src/gallium/winsys/amdgpu/drm/amdgpu_cs.c     |  6 +--
>>   src/gallium/winsys/amdgpu/drm/amdgpu_cs.h     |  4 +-
>>   src/gallium/winsys/radeon/drm/radeon_drm_cs.c |  2 +-
>>   src/gallium/winsys/radeon/drm/radeon_drm_cs.h |  2 +-
>>   6 files changed, 28 insertions(+), 27 deletions(-)
>>
>> diff --git a/src/gallium/drivers/radeon/radeon_winsys.h
>> b/src/gallium/drivers/radeon/radeon_winsys.h
>> index bcd6831ed35..10c63ae4d82 100644
>> --- a/src/gallium/drivers/radeon/radeon_winsys.h
>> +++ b/src/gallium/drivers/radeon/radeon_winsys.h
>> @@ -108,63 +108,64 @@ enum radeon_value_id {
>>       RADEON_VRAM_USAGE,
>>       RADEON_VRAM_VIS_USAGE,
>>       RADEON_GTT_USAGE,
>>       RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
>>       RADEON_CURRENT_SCLK,
>>       RADEON_CURRENT_MCLK,
>>       RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
>>       RADEON_CS_THREAD_TIME,
>>   };
>>   -/* Each group of four has the same priority. */
>>   enum radeon_bo_priority {
>> +    /* Each group of two has the same priority. */
>>       RADEON_PRIO_FENCE = 0,
>>       RADEON_PRIO_TRACE,
>> -    RADEON_PRIO_SO_FILLED_SIZE,
>> +
>> +    RADEON_PRIO_SO_FILLED_SIZE = 2,
>>       RADEON_PRIO_QUERY,
>>         RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
>>       RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
>> -    RADEON_PRIO_DRAW_INDIRECT,
>> +
>> +    RADEON_PRIO_DRAW_INDIRECT = 6,
>>       RADEON_PRIO_INDEX_BUFFER,
>>   -    RADEON_PRIO_CP_DMA = 12,
>> +    RADEON_PRIO_CP_DMA = 8,
>> +    RADEON_PRIO_BORDER_COLORS,
>>   -    RADEON_PRIO_CONST_BUFFER = 16,
>> +    RADEON_PRIO_CONST_BUFFER = 10,
>>       RADEON_PRIO_DESCRIPTORS,
>> -    RADEON_PRIO_BORDER_COLORS,
>>   -    RADEON_PRIO_SAMPLER_BUFFER = 20,
>> +    RADEON_PRIO_SAMPLER_BUFFER = 12,
>>       RADEON_PRIO_VERTEX_BUFFER,
>>   -    RADEON_PRIO_SHADER_RW_BUFFER = 24,
>> +    RADEON_PRIO_SHADER_RW_BUFFER = 14,
>>       RADEON_PRIO_COMPUTE_GLOBAL,
>>   -    RADEON_PRIO_SAMPLER_TEXTURE = 28,
>> +    RADEON_PRIO_SAMPLER_TEXTURE = 16,
>>       RADEON_PRIO_SHADER_RW_IMAGE,
>>   -    RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 32,
>> -
>> -    RADEON_PRIO_COLOR_BUFFER = 36,
>> +    RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 18,
>> +    RADEON_PRIO_COLOR_BUFFER,
>>   -    RADEON_PRIO_DEPTH_BUFFER = 40,
>> +    RADEON_PRIO_DEPTH_BUFFER = 20,
>>   -    RADEON_PRIO_COLOR_BUFFER_MSAA = 44,
>> +    RADEON_PRIO_COLOR_BUFFER_MSAA = 22,
>>   -    RADEON_PRIO_DEPTH_BUFFER_MSAA = 48,
>> +    RADEON_PRIO_DEPTH_BUFFER_MSAA = 24,
>>   -    RADEON_PRIO_SEPARATE_META = 52,
>> +    RADEON_PRIO_SEPARATE_META = 26,
>>       RADEON_PRIO_SHADER_BINARY, /* the hw can't hide instruction cache
>> misses */
>>   -    RADEON_PRIO_SHADER_RINGS = 56,
>> +    RADEON_PRIO_SHADER_RINGS = 28,
>>   -    RADEON_PRIO_SCRATCH_BUFFER = 60,
>> +    RADEON_PRIO_SCRATCH_BUFFER = 30,
>>       /* 63 is the maximum value */
>
>
> 31 is the maximum value ???

Yes. Thanks.

>
>
>
>
>
>>   };
>>     struct winsys_handle;
>>   struct radeon_winsys_ctx;
>>     struct radeon_cmdbuf_chunk {
>>       unsigned cdw;  /* Number of used dwords. */
>>       unsigned max_dw; /* Maximum number of dwords. */
>>       uint32_t *buf; /* The base pointer of the chunk. */
>> @@ -216,21 +217,21 @@ struct radeon_bo_metadata {
>>   };
>>     enum radeon_feature_id {
>>       RADEON_FID_R300_HYPERZ_ACCESS,     /* ZMask + HiZ */
>>       RADEON_FID_R300_CMASK_ACCESS,
>>   };
>>     struct radeon_bo_list_item {
>>       uint64_t bo_size;
>>       uint64_t vm_address;
>> -    uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
>> +    uint32_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
>>   };
>>     struct radeon_winsys {
>>       /**
>>        * The screen object this winsys was created for
>>        */
>>       struct pipe_screen *screen;
>>         /**
>>        * Decrement the winsys reference count.
>> diff --git a/src/gallium/drivers/radeonsi/si_debug.c
>> b/src/gallium/drivers/radeonsi/si_debug.c
>> index 50375ce7cbe..d6207e68d12 100644
>> --- a/src/gallium/drivers/radeonsi/si_debug.c
>> +++ b/src/gallium/drivers/radeonsi/si_debug.c
>> @@ -562,21 +562,21 @@ static void si_dump_bo_list(struct si_context *sctx,
>>                                         (va - previous_va_end) /
>> page_size);
>>                         }
>>                 }
>>                 /* Print the buffer. */
>>                 fprintf(f, "  %10"PRIu64"    0x%013"PRIX64"
>> 0x%013"PRIX64"       ",
>>                         size / page_size, va / page_size, (va + size) /
>> page_size);
>>                 /* Print the usage. */
>>                 for (j = 0; j < 64; j++) {
>
>
>    for (j = 0; j < 32; j++) {

Will do.

Marek


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