[Mesa-dev] [Bug 94747] Convert phi nodes to logical operations

bugzilla-daemon at freedesktop.org bugzilla-daemon at freedesktop.org
Wed Jul 18 06:36:42 UTC 2018


Timothy Arceri <t_arceri at yahoo.com.au> changed:

           What    |Removed                     |Added
         QA Contact|intel-3d-bugs at lists.freedes |mesa-dev at lists.freedesktop.
                   |ktop.org                    |org

--- Comment #2 from Timothy Arceri <t_arceri at yahoo.com.au> ---
As (In reply to Jason Ekstrand from comment #1)
> The code for this already exists.  It's called nir_opt_peephole_select.  The
> only problem is that it only triggers if both sides of the if are empty. 
> I've been wanting to add some sort of heuristic to it for some time now. 
> The only problem is that it's really back-end specific.

Although i965 doesn't use it I believe this is otherwise fixed by the following
commit. We should probably close this bug:

commit 36f0f0318275f65f8744ec6f9471702e2f58e6d5
Author: Eric Anholt <eric at anholt.net>
Date:   Tue Sep 6 19:45:51 2016 -0700

    nir: Allow opt_peephole_sel to be more aggressive in flattening IFs.

    VC4 was running into a major performance regression from enabling control
    flow in the glmark2 conditionals test, because of short if statements
    containing an ffract.

    This pass seems like it was was trying to ensure that we only flattened
    IFs that should be entirely a win by guaranteeing that there would be
    fewer bcsels than there were MOVs otherwise.  However, if the number of
    ALU ops is small, we can avoid the overhead of branching (which itself
    costs cycles) and still get a win, even if it means moving real
    instructions out of the THEN/ELSE blocks.

    For now, just turn on aggressive flattening on vc4.  i965 will need some
    tuning to avoid regressions.  It does looks like this may be useful to
    replace freedreno code.

    Improves glmark2 -b conditionals:fragment-steps=5:vertex-steps=0 from 47
    fps to 95 fps on vc4.

    vc4 shader-db:
    total instructions in shared programs: 101282 -> 99543 (-1.72%)
    instructions in affected programs:     17365 -> 15626 (-10.01%)
    total uniforms in shared programs: 31295 -> 31172 (-0.39%)
    uniforms in affected programs:     3580 -> 3457 (-3.44%)
    total estimated cycles in shared programs: 225182 -> 223746 (-0.64%)
    estimated cycles in affected programs:     26085 -> 24649 (-5.51%)

    v2: Update shader-db output.

    Reviewed-by: Ian Romanick <ian.d.romanick at intel.com> (v1)

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