[Mesa-dev] [PATCH 3/3] radeonsi: emit_spi_map packets optimization

[Marek Olšák]

Hi Sonny,

I've pushed the first 2 patches.

See below for feedback on this patch.

On Tue, Jul 17, 2018 at 10:22 AM, Sonny Jiang <sonny.jiang at amd.com> wrote:
> Signed-off-by: Sonny Jiang <sonny.jiang at amd.com>
> ---
>  src/gallium/drivers/radeonsi/si_build_pm4.h     | 23 +++++++++++++++++++++++
>  src/gallium/drivers/radeonsi/si_gfx_cs.c        |  2 ++
>  src/gallium/drivers/radeonsi/si_state.h         |  1 +
>  src/gallium/drivers/radeonsi/si_state_shaders.c | 20 ++++++++++++--------
>  4 files changed, 38 insertions(+), 8 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_build_pm4.h b/src/gallium/drivers/radeonsi/si_build_pm4.h
> index b339cd5..4fa44f2 100644
> --- a/src/gallium/drivers/radeonsi/si_build_pm4.h
> +++ b/src/gallium/drivers/radeonsi/si_build_pm4.h
> @@ -214,4 +214,27 @@ static inline void radeon_opt_set_context_reg4(struct si_context *sctx, unsigned
>         }
>  }
>
> +/**
> + * Set consecutive registers if any registers value is different.
> + */
> +static inline void radeon_opt_set_context_regn(struct si_context *sctx, unsigned offset,
> +                                              unsigned * value, unsigned num)
> +{
> +       struct radeon_cmdbuf *cs = sctx->gfx_cs;
> +       int i, j;
> +
> +       for (i = 0; i < num; i++) {
> +               if (sctx->tracked_regs.reg_val_seq[i] != value[i]) {
> +                       radeon_set_context_reg_seq(cs, offset, num);
> +                       for (j = 0; j < num; j++) {
> +                               radeon_emit(cs, value[j]);
> +                       }
> +
> +                       memcpy(sctx->tracked_regs.reg_val_seq, value, sizeof(uint32_t) * num);

This function is not reusable in other places, because it always uses
the same reg_val_seq array.

> +
> +                       break;
> +               }
> +       }
> +}
> +
>  #endif
> diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c
> index 628b6c5..cfbcfb0 100644
> --- a/src/gallium/drivers/radeonsi/si_gfx_cs.c
> +++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c
> @@ -353,4 +353,6 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
>                 /* Set all saved registers state to unknown. */
>                 ctx->tracked_regs.reg_saved = 0;
>         }
> +
> +       memset(ctx->tracked_regs.reg_val_seq, 0xff, sizeof(uint32_t) * 32);

A comment why clearing to 0xff is correct would be useful, because
it's not obvious from the first glance.

Marek