[Mesa-dev] [PATCH 2/2] i965: Context aware user space EU control through application

[aravindan.muthukumar at intel.com]

From: "Muthukumar, Aravindan" <aravindan.muthukumar at intel.com>

 The Patch here is to give control to user/ application to really
 decide what's the max GPU load it would put. If that can be
 known in advance, rpcs can be programmed accordingly.
 This solution has changes across i915,
 drm and mesa (not limited only to kernel).

 Here, we pass gpu_load_type = {high, medium, low} from application
 while context is created. Default here is 'High' and applications
 roughly know if they are going to eat up entire GPU. The typical
 usecase of 'Low' is idle screen or minor mouse movements. Users can
 read meaning of high/medium/low for their platform  & then program
 contexts accordingly. Here gpu_load_type directly translates to
 number of shader cores/EUs a particular GPU has.

 Signed-off-by: Aravindan Muthukumar <aravindan.muthukumar at intel.com>
 Signed-off-by: Kedar J Karanje <kedar.j.karanje at intel.com>
 Signed-off-by: Praveen Diwakar <praveen.diwakar at intel.com>
 Signed-off-by: Yogesh Marathe <yogesh.marathe at intel.com>
---
 include/drm-uapi/i915_drm.h             |  8 ++++++++
 src/mesa/drivers/dri/i965/brw_bufmgr.c  | 19 +++++++++++++++++++
 src/mesa/drivers/dri/i965/brw_bufmgr.h  |  4 ++++
 src/mesa/drivers/dri/i965/brw_context.c |  8 +++++++-
 4 files changed, 38 insertions(+), 1 deletion(-)

diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 16e452a..f07c55a 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -319,6 +319,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_I915_PERF_ADD_CONFIG	0x37
 #define DRM_I915_PERF_REMOVE_CONFIG	0x38
 #define DRM_I915_QUERY			0x39
+#define DRM_I915_LOAD_TYPE		0x3d
 
 #define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -377,6 +378,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_PERF_ADD_CONFIG	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
 #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
 #define DRM_IOCTL_I915_QUERY			DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
+#define DRM_IOCTL_I915_LOAD_TYPE        DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_LOAD_TYPE, struct drm_i915_load_type)
 
 /* Allow drivers to submit batchbuffers directly to hardware, relying
  * on the security mechanisms provided by hardware.
@@ -1387,6 +1389,12 @@ struct drm_i915_gem_context_create {
 	__u32 pad;
 };
 
+/* Dynamic Eu control */
+struct drm_i915_load_type {
+	__u32 ctx_id;
+	__u32 load_type;
+};
+
 struct drm_i915_gem_context_destroy {
 	__u32 ctx_id;
 	__u32 pad;
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index 8ba915b..ac74dfd 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -1332,6 +1332,25 @@ brw_create_hw_context(struct brw_bufmgr *bufmgr)
    return create.ctx_id;
 }
 
+/* DYNAMIC EU CONTROL */
+int
+brw_hw_context_load_type(struct brw_bufmgr *bufmgr,
+                        uint32_t ctx_id,
+                        int load_type)
+{
+       struct drm_i915_load_type type = {
+               .ctx_id = ctx_id,
+               .load_type = load_type,
+       };
+       int err;
+
+       err = 0;
+       if(drmIoctl(bufmgr->fd, DRM_IOCTL_I915_LOAD_TYPE, &type))
+               err = -errno;
+
+       return err;
+}
+
 int
 brw_hw_context_set_priority(struct brw_bufmgr *bufmgr,
                             uint32_t ctx_id,
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index 68f5e0c..9e9419b 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -313,6 +313,10 @@ int brw_bo_wait(struct brw_bo *bo, int64_t timeout_ns);
 
 uint32_t brw_create_hw_context(struct brw_bufmgr *bufmgr);
 
+int brw_hw_context_load_type(struct brw_bufmgr *bufmgr,
+                             uint32_t ctx_id,
+                             int load_type);
+
 int brw_hw_context_set_priority(struct brw_bufmgr *bufmgr,
                                 uint32_t ctx_id,
                                 int priority);
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 01a3e16..2ef21b6 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -888,7 +888,8 @@ brwCreateContext(gl_api api,
 
    if (ctx_config->attribute_mask &
        ~(__DRIVER_CONTEXT_ATTRIB_RESET_STRATEGY |
-         __DRIVER_CONTEXT_ATTRIB_PRIORITY)) {
+         __DRIVER_CONTEXT_ATTRIB_PRIORITY |
+         __DRIVER_CONTEXT_ATTRIB_LOAD_TYPE)) {
       *dri_ctx_error = __DRI_CTX_ERROR_UNKNOWN_ATTRIBUTE;
       return false;
    }
@@ -1005,6 +1006,11 @@ brwCreateContext(gl_api api,
          return false;
       }
 
+      if(ctx_config->attribute_mask & __DRIVER_CONTEXT_ATTRIB_LOAD_TYPE) {
+         brw_hw_context_load_type(brw->bufmgr,
+                                  brw->hw_ctx,ctx_config->load_type);
+      }
+
       int hw_priority = GEN_CONTEXT_MEDIUM_PRIORITY;
       if (ctx_config->attribute_mask & __DRIVER_CONTEXT_ATTRIB_PRIORITY) {
          switch (ctx_config->priority) {
-- 
2.7.4