[Mesa-dev] [PATCH 2/3] radeonsi: don't load block dimensions into SGPRs if they are not variable

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/drivers/radeonsi/si_compute.c | 8 ++++----
 src/gallium/drivers/radeonsi/si_compute.h | 3 +--
 src/gallium/drivers/radeonsi/si_shader.c  | 3 ++-
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index 2349be95849..ea6fa3e999d 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -116,24 +116,24 @@ static void si_create_compute_state_async(void *job, int thread_index)
 	sel.info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE] = program->local_size;
 
 	sel.type = PIPE_SHADER_COMPUTE;
 	si_get_active_slot_masks(&sel.info,
 				 &program->active_const_and_shader_buffers,
 				 &program->active_samplers_and_images);
 
 	program->shader.selector = &sel;
 	program->shader.is_monolithic = true;
 	program->uses_grid_size = sel.info.uses_grid_size;
-	program->uses_block_size = sel.info.uses_block_size;
 	program->uses_bindless_samplers = sel.info.uses_bindless_samplers;
 	program->uses_bindless_images = sel.info.uses_bindless_images;
-	program->variable_group_size =
+	program->reads_variable_block_size =
+		sel.info.uses_block_size &&
 		sel.info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
 
 	void *ir_binary = si_get_ir_binary(&sel);
 
 	/* Try to load the shader from the shader cache. */
 	mtx_lock(&sscreen->shader_cache_mutex);
 
 	if (ir_binary &&
 	    si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
 		mtx_unlock(&sscreen->shader_cache_mutex);
@@ -152,21 +152,21 @@ static void si_create_compute_state_async(void *job, int thread_index)
 
 			if (program->ir_type == PIPE_SHADER_IR_TGSI)
 				FREE(program->ir.tgsi);
 			program->shader.selector = NULL;
 			return;
 		}
 
 		bool scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
 		unsigned user_sgprs = SI_NUM_RESOURCE_SGPRS +
 				      (sel.info.uses_grid_size ? 3 : 0) +
-				      (sel.info.uses_block_size ? 3 : 0);
+				      (program->reads_variable_block_size ? 3 : 0);
 
 		shader->config.rsrc1 =
 			S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) |
 			S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8) |
 			S_00B848_DX10_CLAMP(1) |
 			S_00B848_FLOAT_MODE(shader->config.float_mode);
 
 		shader->config.rsrc2 =
 			S_00B84C_USER_SGPR(user_sgprs) |
 			S_00B84C_SCRATCH_EN(scratch_enabled) |
@@ -737,21 +737,21 @@ static void si_setup_tgsi_grid(struct si_context *sctx,
 				radeon_emit(cs, 0);
 			}
 		}
 	} else {
 		if (program->uses_grid_size) {
 			radeon_set_sh_reg_seq(cs, grid_size_reg, 3);
 			radeon_emit(cs, info->grid[0]);
 			radeon_emit(cs, info->grid[1]);
 			radeon_emit(cs, info->grid[2]);
 		}
-		if (program->variable_group_size && program->uses_block_size) {
+		if (program->reads_variable_block_size) {
 			radeon_set_sh_reg_seq(cs, block_size_reg, 3);
 			radeon_emit(cs, info->block[0]);
 			radeon_emit(cs, info->block[1]);
 			radeon_emit(cs, info->block[2]);
 		}
 	}
 }
 
 static void si_emit_dispatch_packets(struct si_context *sctx,
                                      const struct pipe_grid_info *info)
diff --git a/src/gallium/drivers/radeonsi/si_compute.h b/src/gallium/drivers/radeonsi/si_compute.h
index 3a4cdea25ef..ef8b4aec4df 100644
--- a/src/gallium/drivers/radeonsi/si_compute.h
+++ b/src/gallium/drivers/radeonsi/si_compute.h
@@ -46,25 +46,24 @@ struct si_compute {
 	uint64_t active_samplers_and_images;
 
 	unsigned ir_type;
 	unsigned local_size;
 	unsigned private_size;
 	unsigned input_size;
 	struct si_shader shader;
 
 	struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS];
 	unsigned use_code_object_v2 : 1;
-	unsigned variable_group_size : 1;
 	unsigned uses_grid_size:1;
-	unsigned uses_block_size:1;
 	unsigned uses_bindless_samplers:1;
 	unsigned uses_bindless_images:1;
+	bool reads_variable_block_size;
 };
 
 void si_destroy_compute(struct si_compute *program);
 
 static inline void
 si_compute_reference(struct si_compute **dst, struct si_compute *src)
 {
 	if (pipe_reference(&(*dst)->reference, &src->reference))
 		si_destroy_compute(*dst);
 
diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index 405833d3ba7..e05f6ba345a 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -5014,21 +5014,22 @@ static void create_function(struct si_shader_context *ctx)
 			returns[i] = ctx->i32;
 		for (; i < num_returns; i++)
 			returns[i] = ctx->f32;
 		break;
 
 	case PIPE_SHADER_COMPUTE:
 		declare_global_desc_pointers(ctx, &fninfo);
 		declare_per_stage_desc_pointers(ctx, &fninfo, true);
 		if (shader->selector->info.uses_grid_size)
 			add_arg_assign(&fninfo, ARG_SGPR, v3i32, &ctx->abi.num_work_groups);
-		if (shader->selector->info.uses_block_size)
+		if (shader->selector->info.uses_block_size &&
+		    shader->selector->info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
 			ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
 
 		for (i = 0; i < 3; i++) {
 			ctx->abi.workgroup_ids[i] = NULL;
 			if (shader->selector->info.uses_block_id[i])
 				add_arg_assign(&fninfo, ARG_SGPR, ctx->i32, &ctx->abi.workgroup_ids[i]);
 		}
 
 		add_arg_assign(&fninfo, ARG_VGPR, v3i32, &ctx->abi.local_invocation_ids);
 		break;
-- 
2.17.1