[Mesa-dev] [PATCH] radv/gfx9: implement coherent shaders for VK_ACCESS_SHADER_READ_BIT

[Bas Nieuwenhuizen]

Did this pass CTS? If so, woot!

Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>

btw we can avoid some more, I think literally everything on Vega uses
L2 so the VERTEX_ATTRIBUTE_READ, TRANSFER_READ (this one could use CP
DMA, but not for images, and CP DMA can be configured to go through
L2) and INPUT_ATTACHMENT_READ which are pretty much the same should be
OK too.

On Fri, Jul 27, 2018 at 4:14 PM, Samuel Pitoiset
<samuel.pitoiset at gmail.com> wrote:
> Single-sample color and single-sample depth (not stencil)
> are coherent with shaders.
>
> Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
> ---
>  src/amd/vulkan/radv_cmd_buffer.c | 21 ++++++++++++++++++++-
>  1 file changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
> index e0222d0b50..b557f5a92c 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -2022,6 +2022,7 @@ radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
>         bool flush_CB_meta = true, flush_DB_meta = true;
>         enum radv_cmd_flush_bits flush_bits = 0;
>         bool flush_CB = true, flush_DB = true;
> +       bool image_is_coherent = false;
>         uint32_t b;
>
>         if (image) {
> @@ -2034,6 +2035,19 @@ radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
>                         flush_CB_meta = false;
>                 if (!radv_image_has_htile(image))
>                         flush_DB_meta = false;
> +
> +               if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
> +                       if (image->info.samples == 1 &&
> +                           (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
> +                                            VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
> +                           !vk_format_is_stencil(image->vk_format)) {
> +                               /* Single-sample color and single-sample depth
> +                                * (not stencil) are coherent with shaders on
> +                                * GFX9.
> +                                */
> +                               image_is_coherent = true;
> +                       }
> +               }
>         }
>
>         for_each_bit(b, dst_flags) {
> @@ -2045,12 +2059,17 @@ radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
>                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
>                         break;
>                 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
> -               case VK_ACCESS_SHADER_READ_BIT:
>                 case VK_ACCESS_TRANSFER_READ_BIT:
>                 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
>                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
>                                       RADV_CMD_FLAG_INV_GLOBAL_L2;
>                         break;
> +               case VK_ACCESS_SHADER_READ_BIT:
> +                       flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
> +
> +                       if (!image_is_coherent)
> +                               flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
> +                       break;
>                 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
>                         if (flush_CB)
>                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
> --
> 2.18.0
>
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