[Mesa-dev] [PATCH 05/14] radeonsi: don't set VGT_LS_HS_CONFIG if it doesn't change

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/drivers/radeonsi/si_gfx_cs.c     |  1 +
 src/gallium/drivers/radeonsi/si_pipe.h       |  1 +
 src/gallium/drivers/radeonsi/si_state_draw.c | 16 ++++++++++------
 3 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c
index 062856c9bd4..84536b7c6f6 100644
--- a/src/gallium/drivers/radeonsi/si_gfx_cs.c
+++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c
@@ -311,13 +311,14 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
 	ctx->last_restart_index = SI_RESTART_INDEX_UNKNOWN;
 	ctx->last_prim = -1;
 	ctx->last_multi_vgt_param = -1;
 	ctx->last_rast_prim = -1;
 	ctx->last_sc_line_stipple = ~0;
 	ctx->last_vs_state = ~0;
 	ctx->last_ls = NULL;
 	ctx->last_tcs = NULL;
 	ctx->last_tes_sh_base = -1;
 	ctx->last_num_tcs_input_cp = -1;
+	ctx->last_ls_hs_config = -1; /* impossible value */
 
 	ctx->cs_shader_state.initialized = false;
 }
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 9b3a64b81be..6b181f6856a 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -909,20 +909,21 @@ struct si_context {
 	struct r600_resource	*compute_scratch_buffer;
 
 	/* Emitted derived tessellation state. */
 	/* Local shader (VS), or HS if LS-HS are merged. */
 	struct si_shader	*last_ls;
 	struct si_shader_selector *last_tcs;
 	int			last_num_tcs_input_cp;
 	int			last_tes_sh_base;
 	bool			last_tess_uses_primid;
 	unsigned		last_num_patches;
+	int			last_ls_hs_config;
 
 	/* Debug state. */
 	bool			is_debug;
 	struct si_saved_cs	*current_saved_cs;
 	uint64_t		dmesg_timestamp;
 	unsigned		apitrace_call_number;
 
 	/* Other state */
 	bool need_check_render_feedback;
 	bool			decompression_enabled;
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 845ec468aec..42522c01291 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -273,26 +273,30 @@ static void si_emit_derived_tess_state(struct si_context *sctx,
 
 	/* Set userdata SGPRs for TES. */
 	radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
 	radeon_emit(cs, offchip_layout);
 	radeon_emit(cs, ring_va);
 
 	ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
 		       S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
 		       S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
 
-	if (sctx->chip_class >= CIK)
-		radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
-					   ls_hs_config);
-	else
-		radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
-				       ls_hs_config);
+	if (sctx->last_ls_hs_config != ls_hs_config) {
+		if (sctx->chip_class >= CIK) {
+			radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
+						   ls_hs_config);
+		} else {
+			radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
+					       ls_hs_config);
+		}
+		sctx->last_ls_hs_config = ls_hs_config;
+	}
 }
 
 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
 {
 	switch (info->mode) {
 	case PIPE_PRIM_PATCHES:
 		return info->count / info->vertices_per_patch;
 	case SI_PRIM_RECTANGLE_LIST:
 		return info->count / 3;
 	default:
-- 
2.17.0