[Mesa-dev] [PATCH 13/14] radeonsi/gfx9: set POPS_DRAIN_PS_ON_OVERLAP due to a hw bug

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

This may not be needed yet, but let's set it now.
---
 src/gallium/drivers/radeonsi/si_state_binning.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state_binning.c b/src/gallium/drivers/radeonsi/si_state_binning.c
index 5c794376753..9948a95488c 100644
--- a/src/gallium/drivers/radeonsi/si_state_binning.c
+++ b/src/gallium/drivers/radeonsi/si_state_binning.c
@@ -309,21 +309,22 @@ static struct uvec2 si_get_depth_bin_size(struct si_context *sctx)
 }
 
 static void si_emit_dpbb_disable(struct si_context *sctx)
 {
 	struct radeon_winsys_cs *cs = sctx->gfx_cs;
 
 	radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
 			       S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
 			       S_028C44_DISABLE_START_OF_PRIM(1));
 	radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
-			       S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF));
+			       S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF) |
+			       S_028060_POPS_DRAIN_PS_ON_OVERLAP(1));
 }
 
 void si_emit_dpbb_state(struct si_context *sctx)
 {
 	struct si_screen *sscreen = sctx->screen;
 	struct si_state_blend *blend = sctx->queued.named.blend;
 	struct si_state_dsa *dsa = sctx->queued.named.dsa;
 	unsigned db_shader_control = sctx->ps_db_shader_control;
 
 	assert(sctx->chip_class >= GFX9);
@@ -427,12 +428,13 @@ void si_emit_dpbb_state(struct si_context *sctx)
 			       S_028C44_BIN_SIZE_X(bin_size.x == 16) |
 			       S_028C44_BIN_SIZE_Y(bin_size.y == 16) |
 			       S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend.x) |
 			       S_028C44_BIN_SIZE_Y_EXTEND(bin_size_extend.y) |
 			       S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin) |
 			       S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin) |
 			       S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) |
 			       S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
 			       S_028C44_OPTIMAL_BIN_SELECTION(1));
 	radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
-			       S_028060_PUNCHOUT_MODE(punchout_mode));
+			       S_028060_PUNCHOUT_MODE(punchout_mode) |
+			       S_028060_POPS_DRAIN_PS_ON_OVERLAP(1));
 }
-- 
2.17.0