[Mesa-dev] [PATCH 2/6] nv50/ir: add support for SAMP2HND on gk104+ and IMG2HND on gm107+
Rhys Perry
pendingchaos02 at gmail.com
Wed Jun 6 19:55:04 UTC 2018
Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
---
src/gallium/drivers/nouveau/codegen/nv50_ir.cpp | 2 ++
src/gallium/drivers/nouveau/codegen/nv50_ir.h | 2 ++
.../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 22 +++++++++++++++++++
.../drivers/nouveau/codegen/nv50_ir_inlines.h | 4 ++--
.../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 25 ++++++++++++++++++++++
.../nouveau/codegen/nv50_ir_lowering_nvc0.h | 1 +
.../drivers/nouveau/codegen/nv50_ir_print.cpp | 2 ++
.../drivers/nouveau/codegen/nv50_ir_target.cpp | 7 +++---
8 files changed, 60 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
index c987da9908..7c1c76a912 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
@@ -903,6 +903,8 @@ TexInstruction::TexInstruction(Function *fn, operation op)
if (op == OP_TXF)
sType = TYPE_U32;
+ if (op == OP_SAMP2HND || op == OP_IMG2HND)
+ setType(TYPE_U32);
}
TexInstruction::~TexInstruction()
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.h b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
index f4f3c70888..97aa8d1109 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
@@ -134,6 +134,8 @@ enum operation
OP_SUCLAMP, // clamp surface coordinates
OP_SUEAU, // surface effective address
OP_SUQ, // surface query
+ OP_SAMP2HND, // convert bound texture to bindless handle
+ OP_IMG2HND, // convert bound image to bindless handle
OP_MADSP, // special integer multiply-add
OP_TEXBAR, // texture dependency barrier
OP_DFDX,
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 3c5bad05fe..8149c72dd1 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -3570,6 +3570,28 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
handleTXQ(dst0, TXQ_TYPE, 0);
std::swap(dst0[0], dst0[2]);
break;
+ case TGSI_OPCODE_IMG2HND:
+ case TGSI_OPCODE_SAMP2HND:
+ if (!tgsi.getDst(0).isMasked(1))
+ mkOp1(OP_MOV, TYPE_U32, dst0[1], mkImm(0));
+
+ if (!tgsi.getDst(0).isMasked(0)) {
+ bool is_image = tgsi.getOpcode() == TGSI_OPCODE_IMG2HND;
+
+ TexInstruction *texi = new_TexInstruction(
+ func, is_image ? OP_IMG2HND : OP_SAMP2HND);
+ texi->setDef(0, dst0[0]);
+ if (is_image)
+ texi->tex.target = tgsi.getImageTarget();
+ else
+ texi->tex.target = tgsi.getTexture(code, 0);
+ texi->tex.r = tgsi.getSrc(0).getIndex(0);
+ if (tgsi.getSrc(0).isIndirect(0))
+ texi->setIndirectR(fetchSrc(tgsi.getSrc(0).getIndirect(0), 0, NULL));
+
+ bb->insertTail(texi);
+ }
+ break;
case TGSI_OPCODE_FBFETCH:
handleFBFETCH(dst0);
break;
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_inlines.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_inlines.h
index 4cb53ab42e..0262ae9d1f 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_inlines.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_inlines.h
@@ -311,14 +311,14 @@ const FlowInstruction *Instruction::asFlow() const
TexInstruction *Instruction::asTex()
{
- if ((op >= OP_TEX && op <= OP_SULEA) || op == OP_SUQ)
+ if ((op >= OP_TEX && op <= OP_SULEA) || (op >= OP_SUQ && op <= OP_IMG2HND))
return static_cast<TexInstruction *>(this);
return NULL;
}
const TexInstruction *Instruction::asTex() const
{
- if ((op >= OP_TEX && op <= OP_SULEA) || op == OP_SUQ)
+ if ((op >= OP_TEX && op <= OP_SULEA) || (op >= OP_SUQ && op <= OP_IMG2HND))
return static_cast<const TexInstruction *>(this);
return NULL;
}
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 29f674b451..c2cc120147 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -1347,6 +1347,27 @@ NVC0LoweringPass::handleBUFQ(Instruction *bufq)
return true;
}
+bool
+NVC0LoweringPass::handle2HND(TexInstruction *i)
+{
+ assert(targ->getChipset() >= NVISA_GK104_CHIPSET);
+ assert(!i->tex.bindless);
+ bool is_sampler = i->op == OP_SAMP2HND;
+
+ if (is_sampler || targ->getChipset() >= NVISA_GM107_CHIPSET) {
+ //Sampler or image on GM107+
+ uint16_t slot = (is_sampler ? 0 : 32) + i->tex.r;
+ Value *hnd = loadTexHandle(i->getIndirectR(), slot);
+ bld.mkOp1(OP_MOV, TYPE_U32, i->getDef(0), hnd);
+ } else {
+ //Image on NVE4/GK104
+ assert(!"not implemented"); // TODO: Implement for NVE4
+ }
+
+ bld.getBB()->remove(i);
+ return true;
+}
+
void
NVC0LoweringPass::handleSharedATOMNVE4(Instruction *atom)
{
@@ -2928,6 +2949,10 @@ NVC0LoweringPass::visit(Instruction *i)
case OP_SUQ:
handleSUQ(i->asTex());
break;
+ case OP_SAMP2HND:
+ case OP_IMG2HND:
+ handle2HND(i->asTex());
+ break;
case OP_BUFQ:
handleBUFQ(i);
break;
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
index 1b2b36d3cc..f2d67e8d48 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h
@@ -116,6 +116,7 @@ protected:
void handleSharedATOMNVE4(Instruction *);
void handleLDST(Instruction *);
bool handleBUFQ(Instruction *);
+ bool handle2HND(TexInstruction *);
void checkPredicate(Instruction *);
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
index cbb21f5f72..3040372ea7 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
@@ -162,6 +162,8 @@ const char *operationStr[OP_LAST + 1] =
"suclamp",
"sueau",
"suq",
+ "samp2hnd",
+ "img2hnd",
"madsp",
"texbar",
"dfdx",
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
index 298e7c6ef9..32d8dba808 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
@@ -46,7 +46,7 @@ const uint8_t Target::operationSrcNr[] =
1, 1, 1, // TEX, TXB, TXL,
1, 1, 1, 1, 1, 1, 2, // TXF, TXQ, TXD, TXG, TXLQ, TEXCSAA, TEXPREP
1, 1, 2, 2, 2, 2, 2, // SULDB, SULDP, SUSTB, SUSTP, SUREDB, SUREDP, SULEA
- 3, 3, 3, 1, 3, // SUBFM, SUCLAMP, SUEAU, SUQ, MADSP
+ 3, 3, 3, 1, 1, 1, 3, // SUBFM, SUCLAMP, SUEAU, SUQ, SAMP2HND, IMG2HND, MADSP
0, // TEXBAR
1, 1, // DFDX, DFDY
1, 2, 1, 2, 0, 0, // RDSV, WRSV, PIXLD, QUADOP, QUADON, QUADPOP
@@ -111,8 +111,9 @@ const OpClass Target::operationClass[] =
// SULDB, SULDP, SUSTB, SUSTP; SUREDB, SUREDP, SULEA
OPCLASS_SURFACE, OPCLASS_SURFACE, OPCLASS_ATOMIC, OPCLASS_SURFACE,
OPCLASS_SURFACE, OPCLASS_SURFACE, OPCLASS_SURFACE,
- // SUBFM, SUCLAMP, SUEAU, SUQ, MADSP
- OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_ARITH,
+ // SUBFM, SUCLAMP, SUEAU, SUQ, SAMP2HND, IMG2HND, MADSP
+ OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_OTHER,
+ OPCLASS_OTHER, OPCLASS_ARITH,
// TEXBAR
OPCLASS_OTHER,
// DFDX, DFDY, RDSV, WRSV; PIXLD, QUADOP, QUADON, QUADPOP
--
2.14.4
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