[Mesa-dev] [PATCH 4/8] intel/compiler: More peephole select
Matt Turner
mattst88 at gmail.com
Wed Jun 6 23:26:19 UTC 2018
On Wed, Jun 6, 2018 at 2:33 PM, Ian Romanick <idr at freedesktop.org> wrote:
> From: Ian Romanick <ian.d.romanick at intel.com>
>
> Shader-db results:
>
> Skylake and Broadwell had similar results. (Skylake shown)
> total instructions in shared programs: 14371513 -> 14346174 (-0.18%)
> instructions in affected programs: 890389 -> 865050 (-2.85%)
> helped: 3601
> HURT: 1
> helped stats (abs) min: 1 max: 92 x̄: 7.05 x̃: 4
> helped stats (rel) min: 0.10% max: 25.00% x̄: 3.95% x̃: 3.23%
> HURT stats (abs) min: 43 max: 43 x̄: 43.00 x̃: 43
> HURT stats (rel) min: 0.90% max: 0.90% x̄: 0.90% x̃: 0.90%
> 95% mean confidence interval for instructions value: -7.27 -6.80
> 95% mean confidence interval for instructions %-change: -4.05% -3.84%
> Instructions are helped.
>
> total cycles in shared programs: 532435951 -> 532154282 (-0.05%)
> cycles in affected programs: 69203137 -> 68921468 (-0.41%)
> helped: 2654
> HURT: 981
> helped stats (abs) min: 1 max: 4496 x̄: 177.17 x̃: 76
> helped stats (rel) min: <.01% max: 71.34% x̄: 9.16% x̃: 5.42%
> HURT stats (abs) min: 1 max: 33338 x̄: 192.20 x̃: 19
> HURT stats (rel) min: <.01% max: 36.36% x̄: 2.95% x̃: 1.46%
> 95% mean confidence interval for cycles value: -113.38 -41.60
> 95% mean confidence interval for cycles %-change: -6.24% -5.53%
> Cycles are helped.
>
> total spills in shared programs: 8114 -> 8122 (0.10%)
> spills in affected programs: 152 -> 160 (5.26%)
> helped: 0
> HURT: 2
>
> total fills in shared programs: 11082 -> 11100 (0.16%)
> fills in affected programs: 375 -> 393 (4.80%)
> helped: 1
> HURT: 1
>
> Haswell, Ivy Bridge, and Sandy Bridge had similar results. (Ivy Bridge shown)
> total instructions in shared programs: 9897654 -> 9890341 (-0.07%)
> instructions in affected programs: 213092 -> 205779 (-3.43%)
> helped: 775
> HURT: 18
> helped stats (abs) min: 1 max: 65 x̄: 9.62 x̃: 6
> helped stats (rel) min: 0.11% max: 25.00% x̄: 4.85% x̃: 3.70%
> HURT stats (abs) min: 2 max: 20 x̄: 7.89 x̃: 6
> HURT stats (rel) min: 0.70% max: 2.59% x̄: 1.63% x̃: 1.70%
> 95% mean confidence interval for instructions value: -9.93 -8.51
> 95% mean confidence interval for instructions %-change: -5.01% -4.40%
> Instructions are helped.
>
> total cycles in shared programs: 87653348 -> 87562421 (-0.10%)
> cycles in affected programs: 2411339 -> 2320412 (-3.77%)
> helped: 612
> HURT: 227
> helped stats (abs) min: 1 max: 2103 x̄: 162.83 x̃: 53
> helped stats (rel) min: 0.05% max: 58.41% x̄: 6.50% x̃: 2.65%
> HURT stats (abs) min: 1 max: 772 x̄: 38.43 x̃: 10
> HURT stats (rel) min: 0.04% max: 36.36% x̄: 3.60% x̃: 0.92%
> 95% mean confidence interval for cycles value: -128.53 -88.22
> 95% mean confidence interval for cycles %-change: -4.39% -3.14%
> Cycles are helped.
>
> No change on Iron Lake or GM45.
>
> Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
> ---
> src/intel/compiler/brw_nir.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
> index 67c062d91f5..ca9b021767f 100644
> --- a/src/intel/compiler/brw_nir.c
> +++ b/src/intel/compiler/brw_nir.c
> @@ -557,7 +557,21 @@ brw_nir_optimize(nir_shader *nir, const struct brw_compiler *compiler,
> OPT(nir_copy_prop);
> OPT(nir_opt_dce);
> OPT(nir_opt_cse);
> +
> + /* Passing 0 to the peephole select pass causes it to convert
> + * if-statements that contain only move instructions in the branches
> + * regardless of the count.
> + *
> + * Passing 0 to the peephole select pass causes it to convert
> + * if-statements that contain at most a single ALU instruction (total)
> + * in both branches. The select instruction works somewhat differently
> + * on Gen5 and earlier, and adding this pass on those platforms was
It does? Something about min/max requiring the CMP?
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