[Mesa-dev] [PATCH 21/23] intel/eu: Encode and decode native instruction opcodes from/to IR opcodes.
Francisco Jerez
currojerez at riseup.net
Tue Jun 12 02:26:13 UTC 2018
Change brw_inst_set_opcode() and brw_inst_opcode() to call
brw_opcode_encode/decode() transparently in order to translate between
hardware and IR opcodes, and update the EU compaction code in order to
do the same as needed, so we can eventually drop the one-to-one
correspondence between hardware and IR opcodes.
---
src/intel/compiler/brw_eu.h | 13 +++++++++++++
src/intel/compiler/brw_eu_compact.c | 20 +++++++++++++-------
src/intel/compiler/brw_eu_emit.c | 5 +++++
src/intel/compiler/brw_eu_validate.c | 2 +-
src/intel/compiler/brw_inst.h | 8 ++++----
src/intel/compiler/test_eu_compact.cpp | 4 ++--
src/intel/compiler/test_eu_validate.cpp | 2 +-
7 files changed, 39 insertions(+), 15 deletions(-)
diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index dcfaffdaa03..ba8ec04a6ac 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -745,6 +745,19 @@ brw_opcode_decode(const struct gen_device_info *devinfo, unsigned hw)
return desc ? (enum opcode)desc->ir : BRW_OPCODE_ILLEGAL;
}
+static inline void
+brw_inst_set_opcode(const struct gen_device_info *devinfo,
+ brw_inst *inst, enum opcode opcode)
+{
+ brw_inst_set_hw_opcode(devinfo, inst, brw_opcode_encode(devinfo, opcode));
+}
+
+static inline enum opcode
+brw_inst_opcode(const struct gen_device_info *devinfo, const brw_inst *inst)
+{
+ return brw_opcode_decode(devinfo, brw_inst_hw_opcode(devinfo, inst));
+}
+
static inline bool
is_3src(const struct gen_device_info *devinfo, enum opcode opcode)
{
diff --git a/src/intel/compiler/brw_eu_compact.c b/src/intel/compiler/brw_eu_compact.c
index ae14ef10ec0..31cad792125 100644
--- a/src/intel/compiler/brw_eu_compact.c
+++ b/src/intel/compiler/brw_eu_compact.c
@@ -949,7 +949,7 @@ brw_try_compact_3src_instruction(const struct gen_device_info *devinfo,
#define compact_a16(field) \
brw_compact_inst_set_3src_##field(devinfo, dst, brw_inst_3src_a16_##field(devinfo, src))
- compact(opcode);
+ compact(hw_opcode);
if (!set_3src_control_index(devinfo, dst, src))
return false;
@@ -1121,7 +1121,7 @@ brw_try_compact_instruction(const struct gen_device_info *devinfo,
#define compact(field) \
brw_compact_inst_set_##field(devinfo, &temp, brw_inst_##field(devinfo, src))
- compact(opcode);
+ compact(hw_opcode);
compact(debug_control);
if (!set_control_index(devinfo, &temp, src))
@@ -1298,7 +1298,7 @@ brw_uncompact_3src_instruction(const struct gen_device_info *devinfo,
#define uncompact_a16(field) \
brw_inst_set_3src_a16_##field(devinfo, dst, brw_compact_inst_3src_##field(devinfo, src))
- uncompact(opcode);
+ uncompact(hw_opcode);
set_uncompacted_3src_control_index(devinfo, dst, src);
set_uncompacted_3src_source_index(devinfo, dst, src);
@@ -1328,7 +1328,8 @@ brw_uncompact_instruction(const struct gen_device_info *devinfo, brw_inst *dst,
memset(dst, 0, sizeof(*dst));
if (devinfo->gen >= 8 &&
- is_3src(devinfo, brw_compact_inst_3src_opcode(devinfo, src))) {
+ is_3src(devinfo, brw_opcode_decode(
+ devinfo, brw_compact_inst_3src_hw_opcode(devinfo, src)))) {
brw_uncompact_3src_instruction(devinfo, dst, src);
return;
}
@@ -1336,7 +1337,7 @@ brw_uncompact_instruction(const struct gen_device_info *devinfo, brw_inst *dst,
#define uncompact(field) \
brw_inst_set_##field(devinfo, dst, brw_compact_inst_##field(devinfo, src))
- uncompact(opcode);
+ uncompact(hw_opcode);
uncompact(debug_control);
set_uncompacted_control(devinfo, dst, src);
@@ -1578,7 +1579,8 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset,
if ((offset & sizeof(brw_compact_inst)) != 0 && devinfo->is_g4x){
brw_compact_inst *align = store + offset;
memset(align, 0, sizeof(*align));
- brw_compact_inst_set_opcode(devinfo, align, BRW_OPCODE_NENOP);
+ brw_compact_inst_set_hw_opcode(
+ devinfo, align, brw_opcode_encode(devinfo, BRW_OPCODE_NENOP));
brw_compact_inst_set_cmpt_control(devinfo, align, true);
offset += sizeof(brw_compact_inst);
compacted_count--;
@@ -1682,6 +1684,9 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset,
brw_inst_set_imm_ud(devinfo, insn, jump_compacted << shift);
}
break;
+
+ default:
+ break;
}
}
@@ -1693,7 +1698,8 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset,
if (p->next_insn_offset & sizeof(brw_compact_inst)) {
brw_compact_inst *align = store + offset;
memset(align, 0, sizeof(*align));
- brw_compact_inst_set_opcode(devinfo, align, BRW_OPCODE_NOP);
+ brw_compact_inst_set_hw_opcode(
+ devinfo, align, brw_opcode_encode(devinfo, BRW_OPCODE_NOP));
brw_compact_inst_set_cmpt_control(devinfo, align, true);
p->next_insn_offset += sizeof(brw_compact_inst);
}
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 9649ee00b07..d72ad6c19a7 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -2544,6 +2544,8 @@ brw_find_next_block_end(struct brw_codegen *p, int start_offset)
case BRW_OPCODE_HALT:
if (depth == 0)
return offset;
+ default:
+ break;
}
}
@@ -2649,6 +2651,9 @@ brw_set_uip_jip(struct brw_codegen *p, int start_offset)
assert(brw_inst_uip(devinfo, insn) != 0);
assert(brw_inst_jip(devinfo, insn) != 0);
break;
+
+ default:
+ break;
}
}
}
diff --git a/src/intel/compiler/brw_eu_validate.c b/src/intel/compiler/brw_eu_validate.c
index d3189d1ef5e..a5ccc4e0fc8 100644
--- a/src/intel/compiler/brw_eu_validate.c
+++ b/src/intel/compiler/brw_eu_validate.c
@@ -270,7 +270,7 @@ static bool
is_unsupported_inst(const struct gen_device_info *devinfo,
const brw_inst *inst)
{
- return brw_opcode_desc(devinfo, brw_inst_opcode(devinfo, inst)) == NULL;
+ return brw_inst_opcode(devinfo, inst) == BRW_OPCODE_ILLEGAL;
}
static enum brw_reg_type
diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h
index 438a473c1cd..18d010043ae 100644
--- a/src/intel/compiler/brw_inst.h
+++ b/src/intel/compiler/brw_inst.h
@@ -192,7 +192,7 @@ F8(no_dd_check, /* 4+ */ 11, 11, /* 8+ */ 10, 10)
F8(no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9)
F(access_mode, 8, 8)
/* Bit 7 is Reserved (for future Opcode expansion) */
-F(opcode, 6, 0)
+F(hw_opcode, 6, 0)
/**
* Three-source instructions:
@@ -243,7 +243,7 @@ F8(3src_no_dd_clear, 10, 10, 9, 9)
F8(3src_mask_control, 9, 9, 34, 34)
F(3src_access_mode, 8, 8)
/* Bit 7 is Reserved (for future Opcode expansion) */
-F(3src_opcode, 6, 0)
+F(3src_hw_opcode, 6, 0)
/** @} */
#define REG_TYPE(reg) \
@@ -1079,7 +1079,7 @@ F(subreg_index, 22, 18)
F(datatype_index, 17, 13)
F(control_index, 12, 8)
F(debug_control, 7, 7)
-F(opcode, 6, 0) /* Same location as brw_inst */
+F(hw_opcode, 6, 0) /* Same location as brw_inst */
/**
* (Gen8+) Compacted three-source instructions:
@@ -1102,7 +1102,7 @@ FC(3src_dst_reg_nr, 18, 12, devinfo->gen >= 8)
FC(3src_source_index, 11, 10, devinfo->gen >= 8)
FC(3src_control_index, 9, 8, devinfo->gen >= 8)
/* Bit 7 is Reserved (for future Opcode expansion) */
-FC(3src_opcode, 6, 0, devinfo->gen >= 8)
+FC(3src_hw_opcode, 6, 0, devinfo->gen >= 8)
/** @} */
#undef F
diff --git a/src/intel/compiler/test_eu_compact.cpp b/src/intel/compiler/test_eu_compact.cpp
index 702762c194a..7f1f7f4c2be 100644
--- a/src/intel/compiler/test_eu_compact.cpp
+++ b/src/intel/compiler/test_eu_compact.cpp
@@ -74,7 +74,7 @@ clear_pad_bits(const struct gen_device_info *devinfo, brw_inst *inst)
}
if (devinfo->gen == 8 && !devinfo->is_cherryview &&
- is_3src(devinfo, (opcode)brw_inst_opcode(devinfo, inst))) {
+ is_3src(devinfo, brw_inst_opcode(devinfo, inst))) {
brw_inst_set_bits(inst, 105, 105, 0);
brw_inst_set_bits(inst, 84, 84, 0);
brw_inst_set_bits(inst, 36, 35, 0);
@@ -92,7 +92,7 @@ skip_bit(const struct gen_device_info *devinfo, brw_inst *src, int bit)
if (bit == 29)
return true;
- if (is_3src(devinfo, (opcode)brw_inst_opcode(devinfo, src))) {
+ if (is_3src(devinfo, brw_inst_opcode(devinfo, src))) {
if (devinfo->gen >= 9 || devinfo->is_cherryview) {
if (bit == 127)
return true;
diff --git a/src/intel/compiler/test_eu_validate.cpp b/src/intel/compiler/test_eu_validate.cpp
index b132b87a1a3..5de08de12bc 100644
--- a/src/intel/compiler/test_eu_validate.cpp
+++ b/src/intel/compiler/test_eu_validate.cpp
@@ -176,7 +176,7 @@ TEST_P(validation_test, opcode46)
* reserved on Gen 7
* "goto" on Gen8+
*/
- brw_next_insn(p, 46);
+ brw_next_insn(p, brw_opcode_decode(&devinfo, 46));
if (devinfo.gen == 7) {
EXPECT_FALSE(validate(p));
--
2.16.1
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