[Mesa-dev] [PATCH 05/23] intel/eu: Provide desc immediate argument up front to brw_send_indirect_message().

Francisco Jerez currojerez at riseup.net
Tue Jun 12 02:25:57 UTC 2018


The current approach of returning a setup instruction where additional
descriptor fields can be specified is still supported in order to keep
things working, but it will be removed later in this series.
---
 src/intel/compiler/brw_eu.h               |  3 ++-
 src/intel/compiler/brw_eu_emit.c          | 11 ++++++-----
 src/intel/compiler/brw_fs_generator.cpp   |  6 +++---
 src/intel/compiler/brw_vec4_generator.cpp |  4 ++--
 4 files changed, 13 insertions(+), 11 deletions(-)

diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index b2b20713e45..dc7cb500137 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -324,7 +324,8 @@ brw_send_indirect_message(struct brw_codegen *p,
                           unsigned sfid,
                           struct brw_reg dst,
                           struct brw_reg payload,
-                          struct brw_reg desc);
+                          struct brw_reg desc,
+                          unsigned desc_imm);
 
 void brw_ff_sync(struct brw_codegen *p,
 		   struct brw_reg dest,
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 9f449fb9d34..2d7d8c61927 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -2525,7 +2525,8 @@ brw_send_indirect_message(struct brw_codegen *p,
                           unsigned sfid,
                           struct brw_reg dst,
                           struct brw_reg payload,
-                          struct brw_reg desc)
+                          struct brw_reg desc,
+                          unsigned desc_imm)
 {
    const struct gen_device_info *devinfo = p->devinfo;
    struct brw_inst *send;
@@ -2544,7 +2545,7 @@ brw_send_indirect_message(struct brw_codegen *p,
    if (desc.file == BRW_IMMEDIATE_VALUE) {
       setup = p->nr_insn;
       send = next_insn(p, BRW_OPCODE_SEND);
-      brw_set_src1(p, send, desc);
+      brw_set_desc(p, send, desc.ud | desc_imm);
 
    } else {
       struct brw_reg addr = retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD);
@@ -2560,7 +2561,7 @@ brw_send_indirect_message(struct brw_codegen *p,
        * brw_set_*_message() helper functions.
        */
       setup = p->nr_insn;
-      brw_OR(p, addr, desc, brw_imm_ud(0));
+      brw_OR(p, addr, desc, brw_imm_ud(desc_imm));
 
       brw_pop_insn_state(p);
 
@@ -2613,7 +2614,7 @@ brw_send_indirect_surface_message(struct brw_codegen *p,
       surface = addr;
    }
 
-   insn = brw_send_indirect_message(p, sfid, dst, payload, surface);
+   insn = brw_send_indirect_message(p, sfid, dst, payload, surface, 0);
    brw_inst_set_mlen(devinfo, insn, message_len);
    brw_inst_set_rlen(devinfo, insn, response_len);
    brw_inst_set_header_present(devinfo, insn, header_present);
@@ -3370,7 +3371,7 @@ brw_pixel_interpolator_query(struct brw_codegen *p,
                                     GEN7_SFID_PIXEL_INTERPOLATOR,
                                     dest,
                                     mrf,
-                                    vec1(data));
+                                    vec1(data), 0);
    brw_inst_set_mlen(devinfo, insn, msg_length);
    brw_inst_set_rlen(devinfo, insn, response_length);
 
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index 09839d0b4da..2f6258977dc 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -1184,7 +1184,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
 
       /* dst = send(offset, a0.0 | <descriptor>) */
       brw_inst *insn = brw_send_indirect_message(
-         p, BRW_SFID_SAMPLER, dst, src, addr);
+         p, BRW_SFID_SAMPLER, dst, src, addr, 0);
       brw_set_sampler_message(p, insn,
                               0 /* surface */,
                               0 /* sampler */,
@@ -1453,7 +1453,7 @@ fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
       brw_inst *insn = brw_send_indirect_message(
          p, GEN6_SFID_DATAPORT_CONSTANT_CACHE,
          retype(dst, BRW_REGISTER_TYPE_UD),
-         retype(payload, BRW_REGISTER_TYPE_UD), addr);
+         retype(payload, BRW_REGISTER_TYPE_UD), addr, 0);
       brw_set_dp_read_message(p, insn, 0 /* surface */,
                               BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst->exec_size),
                               GEN7_DATAPORT_DC_OWORD_BLOCK_READ,
@@ -1589,7 +1589,7 @@ fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
       /* dst = send(offset, a0.0 | <descriptor>) */
       brw_inst *insn = brw_send_indirect_message(
          p, BRW_SFID_SAMPLER, retype(dst, BRW_REGISTER_TYPE_UW),
-         offset, addr);
+         offset, addr, 0);
       brw_set_sampler_message(p, insn,
                               0 /* surface */,
                               0 /* sampler */,
diff --git a/src/intel/compiler/brw_vec4_generator.cpp b/src/intel/compiler/brw_vec4_generator.cpp
index 386b071cfda..7605ccdc6c5 100644
--- a/src/intel/compiler/brw_vec4_generator.cpp
+++ b/src/intel/compiler/brw_vec4_generator.cpp
@@ -325,7 +325,7 @@ generate_tex(struct brw_codegen *p,
 
       /* dst = send(offset, a0.0 | <descriptor>) */
       brw_inst *insn = brw_send_indirect_message(
-         p, BRW_SFID_SAMPLER, dst, src, addr);
+         p, BRW_SFID_SAMPLER, dst, src, addr, 0);
       brw_set_sampler_message(p, insn,
                               0 /* surface */,
                               0 /* sampler */,
@@ -1393,7 +1393,7 @@ generate_pull_constant_load_gen7(struct brw_codegen *p,
 
       /* dst = send(offset, a0.0 | <descriptor>) */
       brw_inst *insn = brw_send_indirect_message(
-         p, BRW_SFID_SAMPLER, dst, offset, addr);
+         p, BRW_SFID_SAMPLER, dst, offset, addr, 0);
       brw_set_sampler_message(p, insn,
                               0 /* surface */,
                               0 /* sampler */,
-- 
2.16.1



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