[Mesa-dev] [PATCH 01/19] intel: genxml: add mask fields for INSTPM/CS_DEBUG_MODE2 registers

[Lionel Landwerlin]

Those 2 registers have masks on the upper 16bits of field values that
should be applied in HW.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
---
 src/intel/genxml/gen10.xml | 3 +++
 src/intel/genxml/gen11.xml | 3 +++
 src/intel/genxml/gen7.xml  | 4 ++++
 src/intel/genxml/gen75.xml | 4 ++++
 src/intel/genxml/gen8.xml  | 4 ++++
 src/intel/genxml/gen9.xml  | 3 +++
 6 files changed, 21 insertions(+)

diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
index 67fda868193..bb94ea457af 100644
--- a/src/intel/genxml/gen10.xml
+++ b/src/intel/genxml/gen10.xml
@@ -3631,6 +3631,9 @@
     <field name="3D Rendering Instruction Disable" start="0" end="0" type="bool"/>
     <field name="Media Instruction Disable" start="1" end="1" type="bool"/>
     <field name="CONSTANT_BUFFER Address Offset Disable" start="4" end="4" type="bool"/>
+    <field name="3D Rendering Instruction Disable Mask" start="16" end="16" type="bool"/>
+    <field name="Media Instruction Disable Mask" start="17" end="17" type="bool"/>
+    <field name="CONSTANT_BUFFER Address Offset Disable Mask" start="20" end="20" type="bool"/>
   </register>
 
 </genxml>
diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index dea1cd83aec..ef608428730 100644
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -3629,6 +3629,9 @@
     <field name="3D Rendering Instruction Disable" start="0" end="0" type="bool"/>
     <field name="Media Instruction Disable" start="1" end="1" type="bool"/>
     <field name="CONSTANT_BUFFER Address Offset Disable" start="4" end="4" type="bool"/>
+    <field name="3D Rendering Instruction Disable Mask" start="16" end="16" type="bool"/>
+    <field name="Media Instruction Disable Mask" start="17" end="17" type="bool"/>
+    <field name="CONSTANT_BUFFER Address Offset Disable Mask" start="20" end="20" type="bool"/>
   </register>
 
 </genxml>
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 895f5d232b5..3fa3df315ae 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -2621,6 +2621,10 @@
     <field name="3D Rendering Instruction Disable" start="2" end="2" type="bool"/>
     <field name="Media Instruction Disable" start="3" end="3" type="bool"/>
     <field name="CONSTANT_BUFFER Address Offset Disable" start="6" end="6" type="bool"/>
+    <field name="3D State Instruction Disable Mask" start="17" end="17" type="bool"/>
+    <field name="3D Rendering Instruction Disable Mask" start="18" end="18" type="bool"/>
+    <field name="Media Instruction Disable Mask" start="20" end="20" type="bool"/>
+    <field name="CONSTANT_BUFFER Address Offset Disable Mask" start="22" end="22" type="bool"/>
   </register>
 
 </genxml>
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 54362bbb93c..e75f5d78b42 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -3135,6 +3135,10 @@
     <field name="3D Rendering Instruction Disable" start="2" end="2" type="bool"/>
     <field name="Media Instruction Disable" start="3" end="3" type="bool"/>
     <field name="CONSTANT_BUFFER Address Offset Disable" start="6" end="6" type="bool"/>
+    <field name="3D State Instruction Disable Mask" start="17" end="17" type="bool"/>
+    <field name="3D Rendering Instruction Disable Mask" start="18" end="18" type="bool"/>
+    <field name="Media Instruction Disable Mask" start="20" end="20" type="bool"/>
+    <field name="CONSTANT_BUFFER Address Offset Disable Mask" start="22" end="22" type="bool"/>
   </register>
 
 </genxml>
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 24c91e2e578..7edfa8b5cba 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -3374,6 +3374,10 @@
     <field name="3D Rendering Instruction Disable" start="2" end="2" type="bool"/>
     <field name="Media Instruction Disable" start="3" end="3" type="bool"/>
     <field name="CONSTANT_BUFFER Address Offset Disable" start="6" end="6" type="bool"/>
+    <field name="3D State Instruction Disable Mask" start="17" end="17" type="bool"/>
+    <field name="3D Rendering Instruction Disable Mask" start="18" end="18" type="bool"/>
+    <field name="Media Instruction Disable Mask" start="20" end="20" type="bool"/>
+    <field name="CONSTANT_BUFFER Address Offset Disable Mask" start="22" end="22" type="bool"/>
   </register>
 
 </genxml>
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index dbef0726f11..d8407792b72 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -3703,6 +3703,9 @@
     <field name="3D Rendering Instruction Disable" start="0" end="0" type="bool"/>
     <field name="Media Instruction Disable" start="1" end="1" type="bool"/>
     <field name="CONSTANT_BUFFER Address Offset Disable" start="4" end="4" type="bool"/>
+    <field name="3D Rendering Instruction Disable Mask" start="16" end="16" type="bool"/>
+    <field name="Media Instruction Disable Mask" start="17" end="17" type="bool"/>
+    <field name="CONSTANT_BUFFER Address Offset Disable Mask" start="20" end="20" type="bool"/>
   </register>
 
 </genxml>
-- 
2.17.1