[Mesa-dev] [PATCH 06/11] radeonsi: remove references to Evergreen
Marek Olšák
maraeo at gmail.com
Mon Jun 18 23:33:07 UTC 2018
From: Marek Olšák <marek.olsak at amd.com>
---
src/gallium/drivers/radeonsi/si_compute.c | 1 -
src/gallium/drivers/radeonsi/si_dma_cs.c | 2 +-
src/gallium/drivers/radeonsi/si_query.c | 1 -
src/gallium/drivers/radeonsi/si_texture.c | 2 +-
4 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index a66824f37f9..8abdbb74f64 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -950,15 +950,14 @@ static void si_delete_compute_state(struct pipe_context *ctx, void* state){
static void si_set_compute_resources(struct pipe_context * ctx_,
unsigned start, unsigned count,
struct pipe_surface ** surfaces) { }
void si_init_compute_functions(struct si_context *sctx)
{
sctx->b.create_compute_state = si_create_compute_state;
sctx->b.delete_compute_state = si_delete_compute_state;
sctx->b.bind_compute_state = si_bind_compute_state;
-/* ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
sctx->b.set_compute_resources = si_set_compute_resources;
sctx->b.set_global_binding = si_set_global_binding;
sctx->b.launch_grid = si_launch_grid;
}
diff --git a/src/gallium/drivers/radeonsi/si_dma_cs.c b/src/gallium/drivers/radeonsi/si_dma_cs.c
index 1eefaeb6ad5..e632f4e92b8 100644
--- a/src/gallium/drivers/radeonsi/si_dma_cs.c
+++ b/src/gallium/drivers/radeonsi/si_dma_cs.c
@@ -21,21 +21,21 @@
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include "si_pipe.h"
static void si_dma_emit_wait_idle(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->dma_cs;
- /* NOP waits for idle on Evergreen and later. */
+ /* NOP waits for idle. */
if (sctx->chip_class >= CIK)
radeon_emit(cs, 0x00000000); /* NOP */
else
radeon_emit(cs, 0xf0000000); /* NOP */
}
void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
struct r600_resource *dst, struct r600_resource *src)
{
uint64_t vram = ctx->dma_cs->used_vram;
diff --git a/src/gallium/drivers/radeonsi/si_query.c b/src/gallium/drivers/radeonsi/si_query.c
index 9c51c9892e6..db0a723816f 100644
--- a/src/gallium/drivers/radeonsi/si_query.c
+++ b/src/gallium/drivers/radeonsi/si_query.c
@@ -1175,21 +1175,20 @@ static void si_get_hw_query_params(struct si_context *sctx,
params->end_offset = 16;
/* We can re-use the high dword of the last 64-bit value as a
* fence: it is initialized as 0, and the high bit is set by
* the write of the streamout stats event.
*/
params->fence_offset = rquery->result_size - 4;
break;
case PIPE_QUERY_PIPELINE_STATISTICS:
{
- /* Offsets apply to EG+ */
static const unsigned offsets[] = {56, 48, 24, 32, 40, 16, 8, 0, 64, 72, 80};
params->start_offset = offsets[index];
params->end_offset = 88 + offsets[index];
params->fence_offset = 2 * 88;
break;
}
default:
unreachable("si_get_hw_query_params unsupported");
}
}
diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index 7f1eff8f5d9..2103134156d 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -233,21 +233,21 @@ static int si_init_surface(struct si_screen *sscreen,
util_format_description(ptex->format);
bool is_depth, is_stencil;
int r;
unsigned i, bpe, flags = 0;
is_depth = util_format_has_depth(desc);
is_stencil = util_format_has_stencil(desc);
if (!is_flushed_depth &&
ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
- bpe = 4; /* stencil is allocated separately on evergreen */
+ bpe = 4; /* stencil is allocated separately */
} else {
bpe = util_format_get_blocksize(ptex->format);
assert(util_is_power_of_two_or_zero(bpe));
}
if (!is_flushed_depth && is_depth) {
flags |= RADEON_SURF_ZBUFFER;
if (tc_compatible_htile &&
(sscreen->info.chip_class >= GFX9 ||
--
2.17.1
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