[Mesa-dev] [PATCH 11/11] radeonsi: disable DCC statistics gathering on everything but Stoney

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

I think we don't need it on other chips.
---
 src/gallium/drivers/radeonsi/si_clear.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index f366de32d0f..36e2033b1f6 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -450,30 +450,29 @@ static void si_do_fast_color_clear(struct si_context *sctx,
 		 *
 		 * This helps on both dGPUs and APUs, even small APUs like Mullins.
 		 */
 		bool too_small = tex->buffer.b.b.nr_samples <= 1 &&
 				 tex->buffer.b.b.width0 *
 				 tex->buffer.b.b.height0 <= 512 * 512;
 
 		/* Fast clear is the most appropriate place to enable DCC for
 		 * displayable surfaces.
 		 */
-		if (!too_small) {
+		if (sctx->family == CHIP_STONEY && !too_small) {
 			vi_separate_dcc_try_enable(sctx, tex);
 
 			/* RB+ isn't supported with a CMASK clear only on Stoney,
 			 * so all clears are considered to be hypothetically slow
 			 * clears, which is weighed when determining whether to
 			 * enable separate DCC.
 			 */
-			if (tex->dcc_gather_statistics &&
-			    sctx->family == CHIP_STONEY)
+			if (tex->dcc_gather_statistics) /* only for Stoney */
 				tex->num_slow_clears++;
 		}
 
 		/* Try to clear DCC first, otherwise try CMASK. */
 		if (vi_dcc_enabled(tex, 0)) {
 			uint32_t reset_value;
 			bool eliminate_needed;
 
 			if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR))
 				continue;
-- 
2.17.1