[Mesa-dev] [PATCH 3/3] radv: always initialize the clear depth/stencil values to 0
Bas Nieuwenhuizen
bas at basnieuwenhuizen.nl
Wed Jun 20 09:21:11 UTC 2018
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
for the series.
On Tue, Jun 19, 2018 at 4:57 PM, Samuel Pitoiset
<samuel.pitoiset at gmail.com> wrote:
> Similar to the clear color values.
>
> Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 35 ++++++++++++++++++--------------
> src/amd/vulkan/radv_meta_clear.c | 6 +++---
> src/amd/vulkan/radv_private.h | 8 ++++----
> 3 files changed, 27 insertions(+), 22 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
> index d3a6f623f22..240ca8d6f16 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -1217,7 +1217,7 @@ radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
> /**
> * Set the clear depth/stencil values to the image's metadata.
> */
> -void
> +static void
> radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
> struct radv_image *image,
> VkClearDepthStencilValue ds_clear_value,
> @@ -1229,8 +1229,6 @@ radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
>
> va += image->offset + image->clear_value_offset;
>
> - assert(radv_image_has_htile(image));
> -
> if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
> ++reg_count;
> } else {
> @@ -1250,6 +1248,20 @@ radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
> radeon_emit(cs, ds_clear_value.stencil);
> if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
> radeon_emit(cs, fui(ds_clear_value.depth));
> +}
> +
> +/**
> + * Update the clear depth/stencil values for this image.
> + */
> +void
> +radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
> + struct radv_image *image,
> + VkClearDepthStencilValue ds_clear_value,
> + VkImageAspectFlags aspects)
> +{
> + assert(radv_image_has_htile(image));
> +
> + radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
>
> radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
> aspects);
> @@ -3944,9 +3956,11 @@ static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
> assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
> unsigned layer_count = radv_get_layerCount(image, range);
> uint64_t size = image->surface.htile_slice_size * layer_count;
> + VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
> uint64_t offset = image->offset + image->htile_offset +
> image->surface.htile_slice_size * range->baseArrayLayer;
> struct radv_cmd_state *state = &cmd_buffer->state;
> + VkClearDepthStencilValue value = {};
>
> state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
> RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
> @@ -3956,19 +3970,10 @@ static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
>
> state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
>
> - /* Initialize the depth clear registers and update the ZRANGE_PRECISION
> - * value for the TC-compat bug (because ZRANGE_PRECISION is 1 by
> - * default). This is only needed whean clearing Z to 0.0f.
> - */
> - if (radv_image_is_tc_compat_htile(image) && clear_word == 0) {
> - VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
> - VkClearDepthStencilValue value = {};
> -
> - if (vk_format_is_stencil(image->vk_format))
> - aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
> + if (vk_format_is_stencil(image->vk_format))
> + aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
>
> - radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
> - }
> + radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
> }
>
> static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
> diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
> index 44cd0b5c219..075f40e7815 100644
> --- a/src/amd/vulkan/radv_meta_clear.c
> +++ b/src/amd/vulkan/radv_meta_clear.c
> @@ -645,8 +645,8 @@ emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer,
> if (depth_view_can_fast_clear(cmd_buffer, iview, aspects,
> subpass->depth_stencil_attachment.layout,
> clear_rect, clear_value))
> - radv_set_ds_clear_metadata(cmd_buffer, iview->image,
> - clear_value, aspects);
> + radv_update_ds_clear_metadata(cmd_buffer, iview->image,
> + clear_value, aspects);
>
> radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
> .x = clear_rect->rect.offset.x,
> @@ -745,7 +745,7 @@ emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
> iview->image->offset + iview->image->htile_offset,
> iview->image->surface.htile_size, clear_word);
>
> - radv_set_ds_clear_metadata(cmd_buffer, iview->image, clear_value, aspects);
> + radv_update_ds_clear_metadata(cmd_buffer, iview->image, clear_value, aspects);
> if (post_flush) {
> *post_flush |= flush_bits;
> } else {
> diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
> index b4f359374d0..b070066d16d 100644
> --- a/src/amd/vulkan/radv_private.h
> +++ b/src/amd/vulkan/radv_private.h
> @@ -1110,10 +1110,10 @@ void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_sampl
> unsigned radv_cayman_get_maxdist(int log_samples);
> void radv_device_init_msaa(struct radv_device *device);
>
> -void radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
> - struct radv_image *image,
> - VkClearDepthStencilValue ds_clear_value,
> - VkImageAspectFlags aspects);
> +void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
> + struct radv_image *image,
> + VkClearDepthStencilValue ds_clear_value,
> + VkImageAspectFlags aspects);
>
> void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
> struct radv_image *image,
> --
> 2.17.1
>
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