[Mesa-dev] [PATCH 14/19] ac/surface: move cmask_size/alignment into radeon_surf
Timothy Arceri
tarceri at itsqueeze.com
Fri Jun 22 23:13:07 UTC 2018
This does more than moving. Can you add a commit message about why its
safe to change cmask_size from uint64_t -> uint32_t
On 23/06/18 08:32, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> ---
> src/amd/common/ac_surface.c | 6 +++---
> src/amd/common/ac_surface.h | 16 ++++++++--------
> src/amd/vulkan/radv_image.c | 4 ++--
> src/gallium/drivers/radeonsi/si_texture.c | 6 +++---
> 4 files changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
> index 6a335111314..f5f88c1e791 100644
> --- a/src/amd/common/ac_surface.c
> +++ b/src/amd/common/ac_surface.c
> @@ -1279,22 +1279,22 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
> cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode;
> else
> cin.swizzleMode = in->swizzleMode;
>
> ret = Addr2ComputeCmaskInfo(addrlib, &cin, &cout);
> if (ret != ADDR_OK)
> return ret;
>
> surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
> surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
> - surf->u.gfx9.cmask_size = cout.cmaskBytes;
> - surf->u.gfx9.cmask_alignment = cout.baseAlign;
> + surf->cmask_size = cout.cmaskBytes;
> + surf->cmask_alignment = cout.baseAlign;
> }
> }
>
> return 0;
> }
>
> static int gfx9_compute_surface(ADDR_HANDLE addrlib,
> const struct radeon_info *info,
> const struct ac_surf_config *config,
> enum radeon_surf_mode mode,
> @@ -1421,21 +1421,21 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
> surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
>
> surf->num_dcc_levels = 0;
> surf->surf_size = 0;
> surf->fmask_size = 0;
> surf->dcc_size = 0;
> surf->htile_size = 0;
> surf->htile_slice_size = 0;
> surf->u.gfx9.surf_offset = 0;
> surf->u.gfx9.stencil_offset = 0;
> - surf->u.gfx9.cmask_size = 0;
> + surf->cmask_size = 0;
>
> /* Calculate texture layout information. */
> r = gfx9_compute_miptree(addrlib, config, surf, compressed,
> &AddrSurfInfoIn);
> if (r)
> return r;
>
> /* Calculate texture layout information for stencil. */
> if (surf->flags & RADEON_SURF_SBUFFER) {
> AddrSurfInfoIn.flags.stencil = 1;
> diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
> index 864b5bad529..01f1cc8dbac 100644
> --- a/src/amd/common/ac_surface.h
> +++ b/src/amd/common/ac_surface.h
> @@ -143,23 +143,20 @@ struct gfx9_surf_layout {
>
> uint64_t surf_offset; /* 0 unless imported with an offset */
> /* The size of the 2D plane containing all mipmap levels. */
> uint64_t surf_slice_size;
> /* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */
> uint32_t offset[RADEON_SURF_MAX_LEVELS];
>
> uint16_t dcc_pitch_max; /* (mip chain pitch - 1) */
>
> uint64_t stencil_offset; /* separate stencil */
> - uint64_t cmask_size;
> -
> - uint32_t cmask_alignment;
> };
>
> struct radeon_surf {
> /* Format properties. */
> unsigned blk_w:4;
> unsigned blk_h:4;
> unsigned bpe:5;
> /* Number of mipmap levels where DCC is enabled starting from level 0.
> * Non-zero levels may be disabled due to alignment constraints, but not
> * the first level.
> @@ -189,31 +186,34 @@ struct radeon_surf {
> * - DCC (same tile swizzle as color)
> * - FMASK
> * - CMASK if it's TC-compatible or if the gen is GFX9
> * - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9
> */
> uint8_t tile_swizzle;
> uint8_t fmask_tile_swizzle;
>
> uint64_t surf_size;
> uint64_t fmask_size;
> + uint32_t surf_alignment;
> + uint32_t fmask_alignment;
> +
> /* DCC and HTILE are very small. */
> uint32_t dcc_size;
> - uint32_t htile_size;
> + uint32_t dcc_alignment;
>
> + uint32_t htile_size;
> uint32_t htile_slice_size;
> -
> - uint32_t surf_alignment;
> - uint32_t fmask_alignment;
> - uint32_t dcc_alignment;
> uint32_t htile_alignment;
>
> + uint32_t cmask_size;
> + uint32_t cmask_alignment;
> +
> union {
> /* R600-VI return values.
> *
> * Some of them can be set by the caller if certain parameters are
> * desirable. The allocator will try to obey them.
> */
> struct legacy_surf_layout legacy;
>
> /* GFX9+ return values. */
> struct gfx9_surf_layout gfx9;
> diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
> index 24f974ac496..826f898d281 100644
> --- a/src/amd/vulkan/radv_image.c
> +++ b/src/amd/vulkan/radv_image.c
> @@ -765,22 +765,22 @@ radv_image_alloc_fmask(struct radv_device *device,
> static void
> radv_image_get_cmask_info(struct radv_device *device,
> struct radv_image *image,
> struct radv_cmask_info *out)
> {
> unsigned pipe_interleave_bytes = device->physical_device->rad_info.pipe_interleave_bytes;
> unsigned num_pipes = device->physical_device->rad_info.num_tile_pipes;
> unsigned cl_width, cl_height;
>
> if (device->physical_device->rad_info.chip_class >= GFX9) {
> - out->alignment = image->surface.u.gfx9.cmask_alignment;
> - out->size = image->surface.u.gfx9.cmask_size;
> + out->alignment = image->surface.cmask_alignment;
> + out->size = image->surface.cmask_size;
> return;
> }
>
> switch (num_pipes) {
> case 2:
> cl_width = 32;
> cl_height = 16;
> break;
> case 4:
> cl_width = 32;
> diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
> index ef2f9c18fde..4cc8786429a 100644
> --- a/src/gallium/drivers/radeonsi/si_texture.c
> +++ b/src/gallium/drivers/radeonsi/si_texture.c
> @@ -1043,25 +1043,25 @@ void si_print_texture_info(struct si_screen *sscreen,
> u_log_printf(log, " FMASK: offset=%"PRIu64", size=%"PRIu64", "
> "alignment=%u, swmode=%u, epitch=%u\n",
> tex->fmask_offset,
> tex->surface.fmask_size,
> tex->surface.fmask_alignment,
> tex->surface.u.gfx9.fmask.swizzle_mode,
> tex->surface.u.gfx9.fmask.epitch);
> }
>
> if (tex->cmask.size) {
> - u_log_printf(log, " CMask: offset=%"PRIu64", size=%"PRIu64", "
> + u_log_printf(log, " CMask: offset=%"PRIu64", size=%u, "
> "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
> tex->cmask.offset,
> - tex->surface.u.gfx9.cmask_size,
> - tex->surface.u.gfx9.cmask_alignment,
> + tex->surface.cmask_size,
> + tex->surface.cmask_alignment,
> tex->surface.u.gfx9.cmask.rb_aligned,
> tex->surface.u.gfx9.cmask.pipe_aligned);
> }
>
> if (tex->htile_offset) {
> u_log_printf(log, " HTile: offset=%"PRIu64", size=%u, alignment=%u, "
> "rb_aligned=%u, pipe_aligned=%u\n",
> tex->htile_offset,
> tex->surface.htile_size,
> tex->surface.htile_alignment,
>
More information about the mesa-dev
mailing list